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ST10F168
16-BIT MCU WITH 256K BYTE FLASH MEMORY AND 8K BYTE RAM
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HIGH PERFORMANCE CPU - 16-BIT CPU WITH 4-STAGE PIPELINE - 80ns INSTRUCTION CYCLE TIME AT 25MHz CPU CLOCK - 400ns 16 X 16-BIT MULTIPLICATION - 800ns 32 / 16-BIT DIVISION - ENHANCED BOOLEAN BIT MANIPULATION FACILITIES - ADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMS - SINGLE-CYCLE CONTEXT SWITCHING SUPPORT
PQFP144 (28 x 28 mm) (Plastic Quad Flat Pack)
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MEMORY ORGANIZATION - 256K BYTE ON-CHIP FLASH MEMORY - 10K ERASING / PROGRAMMING CYCLES - UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTE WITH CAN) - 2K BYTE ON-CHIP INTERNAL RAM (IRAM) - 6K BYTE ON-CHIP EXTENSION RAM (XRAM) - 20 YEAR DATA RETENTION TIME FAST AND FLEXIBLE BUS - PROGRAMMABLE EXTERNAL BUS CHARACTE- RISTICS FOR DIFFERENT ADDRESS RANGES - 8-BIT OR 16-BIT EXTERNAL DATA BUS - MULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRESS / DATA BUSES - FIVE PROGRAMMABLE CHIP-SELECT SIGNALS - HOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT INTERRUPT - 8-CHANNEL PERIPHERAL EVENT CONTROLLER FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA TRANSFER - 16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 56 SOURCES, SAMPLE-RATE DOWN TO 40ns TIMERS - TWO MULTI-FUNCTIONAL GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS - TWO 16-CHANNEL CAPTURE / COMPARE UNITS. 4-CHANNEL PWM UNIT SERIAL CHANNELS - SYNCHRONOUS / ASYNCHRONOUS SERIAL CHANNEL - HIGH-SPEED SYNCHRONOUS CHANNEL
A/D CONVERTER - 16-CHANNEL 10-BIT - 7.76S CONVERSION TIME FAIL-SAFE PROTECTION - PROGRAMMABLE WATCHDOG TIMER - OSCILLATOR WATCHDOG ON-CHIP CAN 2.0B INTERFACE ON-CHIP BOOTSTRAP LOADER CLOCK GENERATION - ON-CHIP PLL - DIRECT OR PRESCALED CLOCK INPUT. UP TO 111 GENERAL PURPOSE I/O LINES - INDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTION. - PROGRAMMABLE THRESHOLD (HYSTERESIS) IDLE AND POWER DOWN MODES SINGLE VOLTAGE SUPPLY: 5V 10% 144-PIN PQFP PACKAGE
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FLASH XRAM
CPU Core
RAM
PEC
Watchdog
CAPCOM2
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CAPCOM1 P.8
P.0 GPTs ASC EBC PWM ADC SSC P.1 P.4 P.6 P.5
CAN
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Interrupt controller
OSC
BRG P.3
BRG P.7
January 2002
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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ST10F168
TABLE OF CONTENT 1 2 3 4 5 5.1 5.2 5.3 5.4 5.5 6 6.1 7 8 9 10 10.1 10.2 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 INTRODUCTION ......................................................................................................... PIN DATA ................................................................................................................... FUNCTIONAL DESCRIPTION.................................................................................... MEMORY ORGANIZATION........................................................................................ FLASH MEMORY ....................................................................................................... PROGRAMMING / ERASING WITH ST EMBEDDED ALGORITHM KERNEL .......... PROGRAMMING EXAMPLES .................................................................................... FLASH MEMORY CONFIGURATION......................................................................... FLASH PROTECTION ................................................................................................ BOOTSTRAP LOADER MODE ................................................................................... CENTRAL PROCESSING UNIT (CPU) ...................................................................... INSTRUCTION SET SUMMARY................................................................................. EXTERNAL BUS CONTROLLER............................................................................... INTERRUPT SYSTEM ................................................................................................ CAPTURE / COMPARE (CAPCOM) UNIT ................................................................. GENERAL PURPOSE TIMER UNIT ........................................................................... GPT1 ........................................................................................................................... GPT2 ........................................................................................................................... PWM MODULE ........................................................................................................... PARALLEL PORTS .................................................................................................... A/D CONVERTER ....................................................................................................... SERIAL CHANNELS .................................................................................................. CAN MODULE ............................................................................................................ WATCHDOG TIMER ................................................................................................... SYSTEM RESET ......................................................................................................... ASYNCHRONOUS RESET (LONG HARDWARE RESET) ........................................ SYNCHRONOUS RESET (WARM RESET) ............................................................... SOFTWARE RESET ................................................................................................... WATCHDOG TIMER RESET ...................................................................................... RESET CIRCUITRY ................................................................................................... POWER REDUCTION MODES .................................................................................. PAGE 4 5 10 11 13 14 16 18 18 18 19 20 22 23 26 28 28 28 31 32 33 34 36 36 37 37 38 39 39 39 42
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19 19.1 20 20.1 20.2 20.3 20.4 20.5 20.5.1 20.5.2 20.5.3 20.5.4 20.5.5 20.5.6 20.5.7 20.5.8 20.5.9 20.5.10 20.5.11 20.5.12 20.5.13 21 22 SPECIAL FUNCTION REGISTER OVERVIEW.......................................................... IDENTIFICATION REGISTERS .................................................................................. ELECTRICAL CHARACTERISTICS .......................................................................... ABSOLUTE MAXIMUM RATINGS .............................................................................. PARAMETER INTERPRETATION .............................................................................. DC CHARACTERISTICS ............................................................................................ A/D CONVERTER CHARACTERISTICS .................................................................... AC CHARACTERISTICS............................................................................................. Test Waveforms ........................................................................................................ Definition of Internal Timing ......................................................................................... Clock Generation Modes ............................................................................................. Prescaler Operation..................................................................................................... Direct Drive .................................................................................................................. Oscillator Watchdog (OWD) ........................................................................................ Phase Locked Loop ..................................................................................................... External Clock Drive XTAL1 ........................................................................................ Memory Cycle Variables.............................................................................................. Multiplexed Bus ........................................................................................................... Demultiplexed Bus....................................................................................................... CLKOUT and READY.................................................................................................. External Bus Arbitration ............................................................................................... PACKAGE MECHANICAL DATA .............................................................................. ORDERING INFORMATION ....................................................................................... 43 49 50 50 50 50 52 53 53 54 54 55 55 55 55 56 57 57 63 69 71 73 73
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1 - INTRODUCTION The ST10F168 is a derivative of the STMicroelectronics 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high Figure 1 : Logic Symbol peripheral functionality and enhanced I/O capabilities. It also provides on-chip high-speed Flash memory, on-chip high-speed RAM, and clock generation via PLL.
VDD
XTAL1 XTAL2 RSTIN RSTOUT VPP VAREF VAGND NMI EA READY ALE RD WR/WRL Port 5 16-bit ST10F168
VSS
Port 0 16-bit Port 1 16-bit Port 2 16-bit Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit
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2 - PIN DATA
Figure 2 : Pin Configuration (top view)
P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO VDD VSS P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28I0 P7.5/CC29I0 P7.6/CC30I0 P7.7/CC31I0 P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
ST10F168
VAREF VAGND P5.10/AN10/T6EUD P5.11/AN11/T5EUD P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4EUD P5.15/AN15/T2EUD VSS VDD P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO VSS VDD P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IOEX2IN P2.11/CC11IOEX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN/T7IN P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN VSS VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD VSS NMI RSTOUT RSTIN VSS XTAL1 XTAL2 VDD P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 VSS VDD P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 P0H.1/AD9 VSS VDD 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P0H.0/AD8 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2AD2 P0L.1/AD1 P0L.0/AD0 EA ALE READY WR/WRL RD VSS VDD P4.7/A23 P4.6/A22/CAN_TxD P4.5/A21/CAN_RxD P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 VPP/RPD VSS VDD P3.15/CLKOUT P3.13/SCLK P3.12/BHE/WRH P3.11/RXD0 P3.10/TXD0 P3.9/MTSR P3.8/MRST P3.7/T2IN P3.6/T3IN
ST10F168
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Table 1 : Pin Description
Symbol P6.0 - P6.7 Pin 1-8 Type I/O Function 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The following Port 6 pins have alternate functions: P6.0 ... P6.4 P6.5 P6.6 P6.7 CS0 ... CS4 HOLD HLDA BREQ Chip Select 0 Output ... Chip Select 4 Output External Master Hold Request Input Hold Acknowledge Output Bus Request Output
1 ... 5 6 7 8 P8.0 - P8.7 9-16
O ... O I O O I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 8 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). The following Port 8 pins have alternate functions: P8.0 ... P8.7 CC16IO ... CC23IO CAPCOM2: CC16 Capture Input / Compare Output ... CAPCOM2: CC23 Capture Input / Compare Output
9 ... 16 P7.0 - P7.7 19-26
I/O ... I/O I/O
8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 7 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). The following Port 7 pins have alternate functions: P7.0 ... P7.3 P7.4 ... P7.7 POUT0 ... POUT3 CC28IO ... CC31IO PWM Channel 0 Output ... PWM Channel 3 Output CAPCOM2: CC28 Capture Input / Compare Output ... CAPCOM2: CC31 Capture Input / Compare Output
19 ... 22 23 ... 26 P5.0 - P5.9 P5.10 - P5.15 27-36 39-44 39 40 41 42 43 44
O ... O I/O ... I/O I I I I I I I I
16-bit input-only port with Schmitt-Trigger characteristics. The pins of Port 5 can be the analog input channels (up to 16) for the A/D converter, where P5.x equals ANx (Analog input channel x), or they are timer inputs: P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 T6EUD T5EUD T6IN T5IN T4EUD T2EUD GPT2 Timer T6 External Up / Down Control Input GPT2 Timer T5 External Up / Down Control Input GPT2 Timer T6 Count Input GPT2 Timer T5 Count Input GPT1 Timer T4 External Up / Down Control Input GPT1 Timer T2 External Up / Down Control Input
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Table 1 : Pin Description (continued)
Symbol P2.0 - P2.7 P2.8 - P2.15 Pin 47-54 57-64 Type I/O Function 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins have alternate functions: P2.0 ... P2.7 P2.8 CC0IO ... CC7IO CC8IO EX0IN ... P2.15 ... CC15IO EX7IN T7IN CAPCOM: CC0 Capture Input / Compare Output ... CAPCOM: CC7 Capture Input / Compare Output CAPCOM: CC8 Capture Input / Compare Output Fast External Interrupt 0 Input ... CAPCOM: CC15 Capture Input / Compare Output Fast External Interrupt 7 Input CAPCOM2 Timer T7 Count Input
47 ... 54 57
I/O ... I/O I/O I
... 64
... I/O I I
P3.0 - P3.5 P3.6 - P3.13, P3.15
65-70, 73-80, 81
I/O I/O I/O
15-bit (P3.14 is missing) bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 3 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins have alternate functions: P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 T0IN T6OUT CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST MTSR TxD0 RxD0 BHE WRH CAPCOM Timer T0 Count Input GPT2 Timer T6 Toggle Latch Output GPT2 Register CAPREL Capture Input GPT1 Timer T3 Toggle Latch Output GPT1 Timer T3 External Up / Down Control Input GPT1 Timer T4 Input for Count / Gate / Reload / Capture GPT1 Timer T3 Count / Gate Input GPT1 Timer T2 Input for Count / Gate / Reload / Capture SSC Master-Receiver / Slave-Transmitter I/O SSC Master-Transmitter / Slave-Receiver O/I ASC0 Clock / Data Output (Asynchronous / Synchronous) ASC0 Data Input (Asynchronous) or I/O (Synchronous) External Memory High Byte Enable Signal External Memory High Byte Write Strobe SSC Master Clock Output / Slave Clock Input System Clock Output (=CPU Clock)
65 66 67 68 69 70 73 74 75 76 77 78 79
I O I O I I I I I/O I/O O I/O O
80 81
I/O O
P3.13 P3.15
SCLK CLKOUT
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Table 1 : Pin Description (continued)
Symbol P4.0 - P4.7 Pin 85-92 Type I/O Function 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. For external bus configuration, Port 4 can be used to output the segment address lines: P4.0-P4.4 A16-A20 P4.5 A21 CAN_RxD P4.6 A22 CAN_TxD P4.7 A23 Segment Address Line Segment Address Line CAN Receiver Data Input Segment Address Line CAN Transmitter Data Output Most Significant Segment Addrress Line
85-89 90
O O I
91
O O
92 RD WR/WRL 95 96
O O O
External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL mode this pin is activated for low Byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. Ready Input. The active level is programmable. When the Ready function is enabled, the selected inactive level at this pin, during an external memory access, will force the insertion of wait state cycles until the pin returns to the selected active level. Address Latch Enable Output. In case of use of external addressing or of multiplexed mode, this signal is the latch command of the address lines. External Access Enable pin. A low level at this pin during and after Reset forces the ST10F168 to start the program from the external memory space. A high level forces the ST10F168 to start in the internal memory space. Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. In case of an external bus configuration, Port0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.
READY/ READY
97
I
ALE EA
98 99
O I
P0L.0 - P0L.7 100 - 107, P0H.0 108, P0H.1 - P0H.7 111 - 117
I/O
Demultiplexed bus modes
Data Path Width: P0L.0 - P0L.7: P0H.0 - P0H.7: 8-bit D0 - D7 I/O 16-bit D0 - D7 D8 - D15
Multiplexed bus modes
Data Path Width: P0L.0 - P0L.7: P0H.0 - P0H.7: 8-bit AD0 - AD7 A8 - A15 16-bit AD0 - AD7 AD8 - AD15
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Table 1 : Pin Description (continued)
Symbol P1L.0 - P1L.7 P1H.0 - P1H.7 Pin 118-125 128-135 Type I/O Function Two 8-bit bidirectional I/O ports P1L and P1H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following Port1 pins have alternate functions: P1H.4 P1H.5 P1H.6 P1H.7 XTAL1 XTAL2: CC24IO CC25IO CC26IO CC27IO CAPCOM2: CC24 Capture Input CAPCOM2: CC25 Capture Input CAPCOM2: CC26 Capture Input CAPCOM2: CC27 Capture Input
132 133 134 135 XTAL1 XTAL2 138 137
I I I I I O
Oscillator amplifier and internal clock generator input Oscillator amplifier circuit output.
To clock the device from an external source, drive XTAL1 while leaving XTAL2 unconnected. Minimum and maximum high / low and rise / fall times specified in the AC Characteristics must be observed. RSTIN 140 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10F168. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. In bidirectional reset mode (enabled by setting bit BDRSTEN in SYSCON register), the RSTIN line is pulled low for the duration of the internal reset sequence. Internal Reset Indication Output. This pin is set to a low level during hardware, software or watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If bit PWDCFG = `0' in SYSCON register, when the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the ST10F168 to go into power down mode. If NMI is high and PWDCFG ='0', when PWRDN is executed, the part will continue to run in normal mode. If it is not used, pin NMI should be pulled high externally. A/D converter reference voltage. A/D converter reference ground. Flash programming voltage. Programming voltage of the on-chip Flash memory must be supplied to this pin. It is used also as the timing pin for the return from interruptible powerdown mode. Digital Supply Voltage: = + 5V during normal operation and idle mode. > 2.5V during power down mode. Digital Ground.
RSTOUT
141
O
NMI
142
I
VAREF VAGND VPP/RPD
37 38 84
-
VDD
17,46, 56,72, 82,93, 109, 126, 136, 144 18,45, 55,71, 83,94, 110, 127, 139, 143
-
VSS
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3 - FUNCTIONAL DESCRIPTION The architecture of the ST10F168 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. Figure 3 : Block Diagram
16 256K Byte Flash memory 32 CPU-Core 16 Internal RAM
The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F168.
16 6K Byte XRAM PEC 16
Watchdog XTAL1 XTAL2
OSC. + PLL
Interrupt Controller CAN_RxD P4.5 CAN_TxD P4.6 CAN
16
Port 4 Port 1 Port 0
GPT1
ASC usart
CAPCOM2
10-Bit ADC
16
External Bus Controller
CAPCOM1
PWM
SSC
GPT2
16
Port 2 8
16
8
BRG Port 3 15
BRG Port 7 8 Port 8
Port 6 8
Port 5 16
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ST10F168
4 - MEMORY ORGANIZATION The memory space of the ST10F168 is configured in a Von Neumann architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Byte. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. FLASH: 256K Byte of on-chip Flash memory. See Flash Memory on page 13 IRAM: 2K Byte of on-chip internal RAM (dual-port) is provided as a storage for data, system stack, general purpose register banks and code. A register bank is 16 wordwide (R0 to R15) and / or bytewide (RL0, RH0, ..., RL7, RH7) general purpose registers. XRAM: 6K Byte of on-chip extension RAM (single port XRAM) is provided as a storage for data, user stack and code. The XRAM is connected to the internal XBUS and is accessed like an external memory in 16-bit demultiplexed bus-mode without wait state or read / write delay (80ns access at 25MHz CPU clock). Byte and Word access are allowed. The XRAM address range is 00'D000h 00'E7FFh if the XRAM is enabled (XPEN bit 2 of SYSCON register). As the XRAM appears like external memory, it cannot be used for the ST10F168's system stack or register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. If bit XPEN is cleared, then any access in the address range 00'D000h - 00'E7FFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. SFR/ESFR: 1024 Byte (2 x 512 Byte) of address space is reserved for the Special Function Register areas. SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. CAN: Address range 00'EF00h - 00'EFFFh is reserved for the CAN Module access. The CAN is enabled by setting XPEN bit 2 of the SYSCON register. Accesses to the CAN Module use demultiplexed addresses and a 16-bit data bus (Byte accesses are possible). Two wait states give an access time of 160ns at 25MHz CPU clock. No tristate wait state is used. Note: If the CAN module is used, Port 4 can not be programmed to output all 8 segment address lines. Therefore, only 4 segment address lines can be used, reducing the external memory space to 5M Byte (1M Byte per CS line) To meet the needs of designs where more memory is required than is provided on chip, up to 16M Byte of external RAM and / or ROM can be connected to the microcontroller.
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Figure 4 : ST10F168 on-chip memory mapping
0x14 Segment 4 0x13 0x12 0x11 0x10 0x0F Segment 3 0x0E 0x0D 0x0C Segment 2 0x0B 0x0A 0x09 0x08 0x07 Segment 1 0x06 0x05 0x04
0x5'0000
0x4'FFFF 0x4'C000
0x4'8000 0x4'4000 Bank 3 : 96K Byte 0x4'0000 0x3'C000 0x3'8000 0x3'7FFF 0x3'4000 0x3'0000 0x2'C000 Bank 2 : 96K Byte 0x2'8000 0x2'4000 0x2'0000 0x1'FFFF 0x1'C000 Bank 1H : 32K Byte 0x1'8000 0x1'7FFF Bank 1L : 16K Byte 0x1'4000 0x1'3FFF Bank 0 : 16K Byte 0x1'0000 0x0'F600 0x0'FE00 RAM, SFR and X-pheripherals are mapped into the address space. SYSCON.XPEN=1 enables CAN and XRAM (before EINIT)
0x0'FFFF
SFR Area
0x0'FDFF
IRAM : 2K Byte
0x0'F1FF
ESFR Area 0x0'F000
0x0'EFFF
CAN Module 0x0'EF00
Segment 0
0x02 0x01 0x00 Data Page Number
0x0'8000 0x0'7FFF Bank 1L : 16K Byte 0x0'4000 0x0'3FFF Bank 0 : 16K Byte 0x0'0000 Absolute Memory Address
0x0'E7FF
XRAM : 6K Byte 0x0'D000 * Bank 0 and Bank 1 L may be remapped from segment 0 to segment 1 by setting SYSCON.ROMS1 (before EINIT)
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5 - FLASH MEMORY The ST10F168 provides 256K Byte of an electrically erasable and reprogrammable Flash Memory on-chip. The Flash Memory can be used both for code and data storage. It is organized into four 32-bit wide blocks allowing even double Word instructions to be fetched in one machine cycle. The four blocks of size16K, 48K, 96K and 96K Byte can be erased and reprogrammed individually (see Table 2 and Table 3). The Flash Memory can be programmed in a programming board or in the target system which provides high system flexibility. The algorithms to program or erase the flash memory are embedded in the Flash Memory itself (ST Embedded Algorithm Kernel, or STEAKTM). To start a program / erase operation, the user's software has just to load GPRs with the address and data to be programmed, or sector to be erased. STEAK uses embedded routines, which check the validity of the programmed parameters, decode and then execute the programming or erase command. During operation, the STEAK routines carry out checks and retries to verify proper cell programming or erasing. When an error occurs, STEAK returns an error-code which identifies the cause of the error. A Flash Memory protection option prevents the read-back of the Flash Memory contents from external memory, or from on-chip RAM. Code operation from within the Flash continues as normal. The first bank (16K Byte) and part of the second bank (16K Byte out of 48K Byte) of the on-chip Flash Memory of the ST10F168 can be mapped to either segment 0 (addresses 00000h to 07FFFh) or to segment 1 (addresses 10000h to 17FFFh) during the initialization phase. External memory can be used for additional system flexibility.
VDD = 5V 10%, VPP = 12V 5%, VSS = 0V, fCPU = 25MHz, for Q6 version : TA = -40C, +85C and for Q3 version TA = -40C, + 125C. Table 2 : Flash Memory Characteristics
Symbol fCPU Cyc tSPRG tDPRG tEBNK tRET Parameter CPU Frequency during erasing / programming operation Erasing / Programming Cycles Single Word Programming Time Double Word Programming Time Sector Erasing Time Data Retention Time fCPU = 25MHz fCPU = 25MHz fCPU = 25MHz fCPU = 25MHz Defectivity below 1ppm / year Test Conditions Min. 5 20 Typ. 40 40 3 Max. 32 10K 1500 1500 15 s s s year Unit MHz
Table 3 : Flash Memory Bank Organisation
Bank 0 1 2 3 Addresses (segment 0) 000000h to 003FFFh 004000h to 007FFFh + 018000h to 01FFFFh 020000h to 037FFFh 038000h to 04FFFFh Addresses (segment 1) 010000h to 013FFFh 014000h to 01FFFFh 020000h to 03FFFFh 038000h to 04FFFFh Size (Byte) 16K 48K 96K 96K
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5.1 - Programming / Erasing with ST Embedded Algorithm Kernel There are three stages to run STEAK : - To load the registers R0 to R4 with the STEAK command, the address and the data to be programed, or sector to be erased. Table 4 gives the STEAK parameters for each type of Flash programming / erasing operation. Table 5 defines the codes used in Table 4. - To initiate the Unlock Sequence. The Unlock Sequence is composed of two consecutive writes to an even address in the Flash active address space - the first write has direct addressing mode (MOV mem, Rwn) - the second write has indirect addressing mode (MOV [Rwm], Rwn). Rwn can be any unused Word-GPR (R6 to R15) loaded with a value resulting in the same even address as "mem". Table 4 : STEAK parameters
Command Single Word programming Double Word programming Multiple (block) programming Sector Erasing Set Flash Protection UPROG bit Read Status R0 55Ash DD4sh AA5sh EEEEh CCCCh 7777h R1 AddOff AddOff BegAddOff 5555h 5555h nu R2 W DWL EndAddOff Bnk 3333h nu R3 nu DWH SourceAddr Bnk AAAAh nu R4 2TCL 2TCL 2TCL 2TCL 2TCL 2TCL
- To read the return values in R0. When the embedded programming / erasing algorithm returns to trigger point, return values are given in R0. Table 6 gives the error-code definitions, Table 7 gives the return values in each register for each type of Flash programming / erasing command. Note: The Flash Embedded STEAK Algorithms require at least 50 words on the Internal System Stack. STEAK verifies that there is enough free space on the System Stack, before performing a programming or erasing operation.The MDH, MDL and MDC register content are modified. Code examples for programming and erasing the Flash Memory using STEAK are given in Section 5.2. Note For more details refer to STEAK application note on www.st.com web site.
Table 5 : Programming / erasing code definition
s AddOff W Segment of the Target Flash Memory cell, Segment Offset of the Target Flash Memory cell. Must be even value (Word-aligned address). Data (Word) to be written in Flash.
DWL,DWH Data (double Word, DHL = low Word, DWH = high Word) to be written in Flash. BegAddOff Segment Offset of the FIRST Target Flash Memory Word to be written in a Multiple programming command. Must be even value (Word-aligned address).
Segment Offset of the LAST Target Flash Memory Word to be written in a Multiple programming command. EndAddOff Must be even value (Word-aligned address). The value D = (EndAddOff - BegAddOff) must be: 0 <= D < 16384 (ie. up to one page (16K Byte) can be written in the flash with one multi-Word programming command). Start address for the block to be programmed. This address is using implicitly the data paging mechanism of the CPU. SourceAdd value must respect the following rules : SourceAdd - SourceAdd + (EndAddOff - BegAddOff) < 16384. - Page 0 and 1 can NOT be used for source data if bit ROMS1 = `1' (in SYSCON register). Note that source data can be located in Flash (In pages 0, 1, 6 to 19 if bit ROMS1 = `0', or in pages 4 to 19 if bit ROMS1 = `1'). Bnk 2TCL Number of the Bank to be erased. For security, R2 and R3 must hold the same value. CPU clock period in nano-seconds (eg. R4 = 50 (32h) means CPU frequency is 20MHz).
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Table 6 : Error Code Definition (R0 content after STEAK execution)
Error Code 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch FFh Operation was successful Flash Protection is active Vpp voltage not present Programming operation failed Address value (R1) incorrect: not in Flash address area or odd CPU period out of range (must be between 30 ns to 500 ns) Not enough free space on system stack for proper operation Incorrect bank number (R2,R3) specified Erase operation failed (phase 1) Bad source address for Multiple Word programming command Bad number of words to be copied in Multiple Word programming command: one destination will be out of flash. PLL Unlocked or Oscillator watchdog overflow occured during programming or erasing the flash. Erase operation failed (phase 2) Unknown or bad command Meaning
Table 7 : Return values for each programming / erase command
Programming Command Single or double Word programming Block programming Erasing After status read R0 Error code R1 Unchanged R2 Data in Flash for location Segment + Segment Offset (R0.[3:0] with R1) R3 R4-R15
Data in Flash for Unchanged location Segment + Segment Offset + 2 (R0[3:0] with R1+2) Unchanged
Error The last segment offset address of the Undefined code last written Word in Flash (failing Flash address if R0 is not equal to zero) Error code Error Flash embedded rev code MSByte = major release LSByte = minor revision Undefined Circuit identifiers : R2 = #0787h R3 = #0101h for this device
Unchanged Unchanged
Note: The Flash Embedded STEAK Algorithms require at least 50 words on the Internal System Stack for proper operation. The program itself verifies that there is enough free space on the System Stack before performing a programming or erasing operation, by computing the Word number between Stack Pointer (SP) and Stack Overflow register (STKOV ). The MDH, MDL and MDC register content are modified. Registers R0 to R4 are used as Input Data for STEAK, and are modified as explained above (Return Values).
Registers R5 to R15 are used internally by STEAK, but preserved on entry and restore on exit of STEAK. IT IS VERY IMPORTANT TO TAKE INTO ACCOUNT THE FACT THAT STEAK USES UP TO 50 WORDS ON THE SYSTEM STACK. TO PREVENT ANY ABNORMAL SITUATION, IT IS VERY IMPORTANT TO INITIALIZE CORRECTLY THE STACK SIZE TO AT LEAST 64 WORDS, AND TO CORRECTLY INITIALIZE REGISTER STKOV.
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5.2 - Programming Examples Programming a double Word ; code shown below assumes that Flash is mapped in segment 1 ; ie. bit ROMS1 = `1' in SYSCON register ; Flash must be enabled, ie. bit ROMEN = `1' in SYSCON. MOV OR MOV MOV MOV MOV MOV R0, #0DD40h R0, #01h R1, #00224h R2, #03456h R3, #04567h R4, #050d R7, #08000h ; DD4xh : Double Word programming command ; Selects segment 1 in flash memory ; Address to be programmed is 01'0224h ; Data to be programmed at 01'0224h ; Data to be programmed at 01'0226h ; 50ns is 20MHz CPU clock frequency ; R7 used for Flash trigger sequence
#define FCR 08000h ; Flash Unlock Sequence consists in two consecutive writes, with the direct addressing mode and then the indirect addressing mode. FCR must represent an even address in the active address space of the Flash memory, and Rwn can be any unused Word GPR (R6 to R15)loaded with a value resulting in the same even address than FCR EXTS MOV MOV NOP NOP #1, #2 FCR, R7 [R7], R7 ; Flash can be mapped in segment 0 or 1 ; first part ; second part ; WARNING: place 2 NOP operations after ; the Unlock sequence to avoid all possible ; pipeline conflicts in STEAK programs Note: For easier coding, the standard data paging addressing scheme is overriden for the two MOV instructions of the Flash Trigger Sequence (EXTS instruction). However this coding also locks both standard and PEC interrupts and class A hardware traps. This override can be replaced by an ATOMIC instruction if the standard DPP addressing scheme must be preserved.
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Programming a block of data The following code is provided as an example to program a block of data. Flash to be programmed is from address 01'9000h to 01'9FFEh (included). Source data (data to be copied into flash) is located in external RAM from address 05'1000h (to 05'1FFEh, implicitly) : ; code shown below assumes that flash is mapped in segment 1 ; ie. bit ROMS1 = `1' in SYSCON register ; Flash must be enabled, ie. bit ROMEN = `1' in SYSCON. MOV OR MOV MOV MOV SCXT R0, #0AA50h R0, #01h R1, #09000h R2, #09FFEh R3, #09000h DPP2,#20d ; AA5xh : Multi Word programming command ; Selects segment 1 in Flash memory ; First Flash Segment Offset Address ; Last Flash Segment Offset Address ; Source data address: use DPP2 as ; data page pointer ; Source is in page 20 (first page of ; segment 5): save previous DPP2 value ; and load it with source page number MOV MOV EXTS MOV MOV NOP NOP POP DPP2 R4, #050d R7, #08000h #1, #2 FCR, R7 [R7], R7 ; 50ns is 20MHz CPU clock frequency ; R7 used for Flash trigger sequence ; Flash can be mapped in segment 0 or 1 ; first part ; second part ; WARNING: place 2 NOP operations after ; the Unlock sequence to avoid all possible ; pipeline conflicts in STEAK programs ; restore DPP2
#define FCR 08000h
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5.3 - Flash Memory Configuration The default memory configuration of the ST10F168 Memory is determined by the state of the EA pin at reset. This value is stored in the Internal ROM Enable bit : ROMEN of the SYSCON Register. When ROMEN = 0, the internal FLASH is disabled and external ROM is used for startup control. Flash memory can be enabled later by setting the ROMEN bit of SYSCON to 1. Ensure that the code which performs this setting is NOT running from external ROM in a segment that will be replaced by FLASH memory, otherwise unexpected behaviour may occur. For example, if the external ROM code is located in the first 32K Byte of segment 0, the first 32K Byte of the FLASH must then be enabled in segment 1. This is done by setting the ROMS1 bit of SYSCON to 0, before or simultaneously with setting the ROMEN bit. This must be done in the externally supplied program, before the execution of the EINIT instruction. If program execution starts from external memory, but the Flash memory mapped in segment 0 is accessed later, then the code that sets the ROMEN bit must be executed either in segment 0 but above address 00'8000h, or from the internal RAM. Bit ROMS1 only affects the mapping of the first 32K Byte of the Flash memory. All other parts of the Flash memory (addresses 01'8000h 04'FFFFh) remain unaffected. Note: The SGTDIS Segmentation Disable / Enable must also be set to 0 to enable the use of the full 256K Byte of on-chip memory in addition to the external boot memory. The correct procedure for changing the segmentation registers must be observed to prevent an unwanted trap condition : - Instructions that configure the internal memory must only be executed from external memory or from the internal RAM. - An Absolute Inter-Segment Jump (JMPS) instruction must be executed after Flash enabling, before the next instruction, even if the next instruction is located in the consecutive address. - Whenever the internal memory is disabled, enabled or remapped, the DPPs must be explicitly (re)loaded to enable correct data accesses to the internal memory and / or external memory. 5.4 - Flash Protection If Flash Protection is active, data operands in the on-chip Flash Memory area can only be read by a program executed from the Flash Memory itself.
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Program branches from or into the on-chip Flash memory are possible in the Flash protection mode. Erasing and programming of the Flash memory is not possible as long as protection is active. Flash protection is controlled by the Protection UPROM Programming Bit (UPROG). UPROG is a 'hidden' one-time programmable bit only accessible in a special mode which can be entered via a Flash EPROM programming board for example. If UPROG is set to "1", Flash protection is active after reset. By default Flash Protection is disabled (UPROG=0). When flash protection is active (the default after reset if UPROG bit is set), then any read access in the flash by a code executed from external or internal RAM (IRAM or XRAM) will return the value 0B88Bh. Any call of STEAK will return the error code `01' (Protected flash). Normally Flash protection should never be deactivated, once activated. If this has to be done, for example because the Flash memory has to be reprogrammed with updated program / variables, a zero value has to be written at any even address in the active address space of the Flash memory. This write can be done only by an instruction executed from the internal Flash Memory itself. For example: MOV FLASH,ZEROS ; Deactivate Flash Protection. ; Flash is any even address in Flash memory space. This instruction MUST be executed from Flash memory itself. After this instruction, the flash is temporarily de-protected, thus any read access of the flash from code executed from external memory or internal RAMs will be correctly executed, and calls of STEAK can be correctly performed (programming, erasing or status reading). Note: 1. That all STEAK commands re-activate the flash protection if bit UPROG is set when completed. 5.5 - Bootstrap Loader Mode Pin P0L.4 (BSL) activates the on-chip bootstrap loader, when low during hardware reset. The bootstrap loader allows moving the start code into the internal RAM of the ST10F168 via the serial interface ASC0. The ST10F168 will remain in bootstrap loader mode until a hardware reset with P0L.4 high or a software reset occurs. The bootstraps loader acknowledge byte is D5h.
ST10F168
6 - CENTRAL PROCESSING UNIT (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10F168's instructions can be executed in one instruction cycle which requires 62.5ns at 32MHz CPU clock. For example, shift and rotate instructions are processed in one instruction cycle independent of the number of bit to be shifted. Multiple-cycle instructions have been optimized: branches are carried out in 2 cycles, 16 x 16-bit multiplication in 5 cycles and a 32/16 bit division in 10 cycles.The jump cache reduces the execution time of repeatedly performed jumps in a loop, from 2 cycles to 1 cycle. Figure 5 : CPU Block Diagram
Internal RAM 2K Byte
The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others. A system stack of up to 2048 Byte stores temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value on each stack access, for the detection of a stack overflow or underflow.
CPU SP STKOV STKUN Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline 32 PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs MDH MLD Mul./Div.-HW Bit-Mask Gen. General Purpose Registers R15
256K Byte Flash memory
Bank n
ALU 16-Bit Barrel-Shift CP ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr.
R0
Bank i
16 16 Bank 0
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6.1 - Instruction Set Summary The Table 8 lists the instructions of the ST10F168. The various addressing modes, instruction operation, parameters for conditional execution of Table 8 : Instruction set summary
Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL/SHR ROL/ROR ASHR MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC Add Word (Byte) operands Add Word (Byte) operands with Carry Subtract Word (Byte) operands Subtract Word (Byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16 x 16-bit) (Un)Signed divide register MDL by direct GPR (16 / 16-bit) (Un)Signed long divide register MD by direct GPR (32 / 16-bit) Complement direct Word (Byte) GPR Negate direct Word (Byte) GPR Bitwise AND, (Word / Byte operands) Bitwise OR, (Word / Byte operands) Bitwise XOR, (Word / Byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND / OR / XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high / low Byte of bit-addressable direct Word memory with immediate data Compare Word (Byte) operands Compare Word data to GPR and decrement GPR by 1/2 Compare Word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct Word GPR and store result in direct Word GPR Shift left / right direct Word GPR Rotate left / right direct Word GPR Arithmetic (sign bit) shift right direct Word GPR Move Word (Byte) data Move Byte operand to Word operand with sign extension Move Byte operand to Word operand. with zero extension Jump absolute / indirect / relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Description Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 2/4 2/4 2/4 4 4 4 4
instructions, opcodes and a detailed description of each instruction can be found in the "ST10 Family Programming Manual".
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Table 8 : Instruction set summary
Mnemonic JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Description Jump relative and set bit if direct bit is not set Call absolute / indirect / relative subroutine if condition is met Call absolute subroutine in any code segment Push direct Word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push / pop direct Word register onto / from system stack Push direct Word register onto system stack and update register with Word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct Word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
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7 - EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required, or to one of four different external memory access modes : - 16 / 18 / 20 / 24-bit addresses and 16-bit data, demultiplexed. - 16 / 18 / 20 / 24-bit addresses and 16-bit data, multiplexed. - 16 / 18 / 20 / 24-bit addresses and 8-bit data, multiplexed. - 16 / 18 / 20 / 24-bit addresses and 8-bit data, demultiplexed. In demultiplexed bus modes addresses are output on Port1 and data are input / output on Port0 or P0L, respectively. In the multiplexed bus modes both addresses and data use Port0 for input / output. Timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ALE and read / write delay) are programmable giving the choice of a wide range of memories and external peripherals. Up to 4 independent address windows may be defined (using register pairs ADDRSELx / BUSCONx) to access different resources and bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. Access to very slow memories is supported by a `Ready' function. A HOLD/HLDA protocol is available for bus arbitration which shares external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In master mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to'1' the slave mode is selected where pin HLDA is switched to input. This directly connects the slave controller to another master controller without glue logic. For applications which require less external memory space, the address space can be restricted to 1M Byte, 256K Byte or to 64K Byte. Port4 outputs all 8 address lines if an address space of 16M Byte is used, otherwise four, two or no address lines. Chip select timing can be programmed. By default (after reset), the CSx lines change half a CPU clock cycle after the rising edge of ALE. With the CSCFG bit set in the SYSCON register the CSx lines can change with the rising edge of ALE. The active level of the READY pin can be set by bit RDYPOLx in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOLx in the associated BUSCONx register.
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8 - INTERRUPT SYSTEM The interrupt response time for internal program execution is from 157ns to 375ns at 32MHz CPU clock. The ST10F168 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller. Any of these interrupt requests can be serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single Byte or Word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited to perform the transmission or the reception of blocks of data. Table 9 : Interrupt sources
Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 Request Flag CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT Vector Location 00'0040h 00'0044h 00'0048h 00'004Ch 00'0050h 00'0054h 00'0058h 00'005Ch 00'0060h 00'0064h 00'0068h 00'006Ch 00'0070h 00'0074h 00'0078h 00'007Ch 00'00C0h 00'00C4h Trap Number 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 30h 31h 23/74
The ST10F168 has 8 PEC channels, each of them offers such fast interrupt-driven data transfer capabilities. A interrupt control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield is dedicated to each existing interrupt source. Thanks to its related register, each source can be programmed to one of sixteen interrupt priority levels. Once starting to be processed by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 9 shows all the available ST10F168 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
ST10F168
Table 9 : Interrupt sources (continued)
Source of Interrupt or PEC Service Request CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D Conversion Complete A/D Overrun Error ASC0 Transmitter ASC0 Transmitter Buffer ASC0 Receiver ASC0 Error SSC Transmitter SSC Receiver SSC Error PWM Channel 0...3 CAN Interface X-Peripheral Node X-Peripheral Node PLL Unlock Request Flag CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR CC30IR CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR T6IR CRIR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR PWMIR XP0IR XP1IR XP2IR XP3IR Enable Flag CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE CC30IE CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE PWMIE XP0IE XP1IE XP2IE XP3IE Interrupt Vector CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT CC30INT CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT PWMINT XP0INT XP1INT XP2INT XP3INT Vector Location 00'00C8h 00'00CCh 00'00D0h 00'00D4h 00'00D8h 00'00DCh 00'00E0h 00'00E4h 00'00E8h 00'00ECh 00'00F0h 00'0110h 00'0114h 00'0118h 00'0080h 00'0084h 00'00F4h 00'00F8h 00'0088h 00'008Ch 00'0090h 00'0094h 00'0098h 00'009Ch 00'00A0h 00'00A4h 00'00A8h 00'011Ch 00'00ACh 00'00B0h 00'00B4h 00'00B8h 00'00BCh 00'00FCh 00'0100h 00'0104h 00'0108h 00'010Ch Trap Number 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 44h 45h 46h 20h 21h 3Dh 3Eh 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 47h 2Bh 2Ch 2Dh 2Eh 2Fh 3Fh 40h 41h 42h 43h
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Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any other program execution. Hardware trap services cannot not be interrupted by standard interrupt or by PEC interrupts. Table 10 shows all of the possible exceptions or error conditions that can arise during run-time :
Table 10 : Exceptions or error conditions that can arise during run-time
Exception Condition Reset Functions Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction UNDOPC PRTFLT ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [2Ch -3Ch] 0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh] I I I I I NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00'0008h 00'0010h 00'0018h 02h 04h 06h II II II RESET RESET RESET 00'0000h 00'0000h 00'0000h 00h 00h 00h III III III Trap Flag Trap Vector Vector Location Trap Number Trap Priority
Any [00'0000h- 00'01FCh] Any [00h - 7Fh] Current CPU in steps of 4h Priority
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9 - CAPTURE / COMPARE (CAPCOM) UNIT The ST10F168 has two 16 channel CAPCOM units which support generation and control of timing sequences on up to 32 channels with a maximum resolution of 320ns at 32MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture / compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow / underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture / compare registers relative to external events. Each of the two capture / compare register arrays contain 16 dual purpose capture / compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare functions. Each register has one associated port pin which serves as an input pin for triggering the capture function, or as an output Table 11 : Compare Modes
Compare Modes Mode 0 Mode 1 Mode 2 Mode 3 Function Interrupt-only compare mode ; several compare interrupts per timer period are possible. Pin toggles on each compare match ; several compare events per timer period are possible. Interrupt-only compare mode ; only one compare interrupt per timer period is generated. Pin set `1' on match; pin reset `0' on compare time overflow ; only one compare event per timer period is generated.
pin (except for CC24...CC27) to indicate the occurrence of a compare event. When a capture / compare register has been selected for capture mode, the current contents of the allocated timer will be latched (captured) into the dedicated capture / compare register in response to an external event at the corresponding port pin which is associated with this register. In addition, a specific interrupt request for this capture / compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all the registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture / compare register, specific actions will be taken based on the selected compare mode. The input frequencies fTx, for the timer input selector Txl, are determined as a function of the CPU clock. The timer input frequencies, the resolution and the periods which result from the selected pre-scaler option in TxI when using a 25MHz CPU clock are listed in the Table 12. The numbers of the timer periods are based on a reload value of 0000h. Note that some numbers are rounded to 3 significant figures.
Double Register Mode Two registers operate on one pin; pin toggles on each compare match ; several compare events per timer period are possible.
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Table 12 : CAPCOM timer input frequencies, resolution and periods
Timer Input Selection TxI
fCPU = 25MHz
000b fCPU pre-scaler Input Frequency Resolution Period 8 001b 16 010b 32 781KHz 1.28s 83.9ms 011b 64 391KHz 2.56s 167ms 100b 128 195KHz 5.12s 336ms 101b 256 97.7KHz 10.24s 671ms 110b 512 48.8KHz 20.48s 1.34s 111b 1024 24.4KHz 40.96s 2.68s
3.125MHz 1.56MHz 320ns 21.0ms 640ns 41.9ms
Table 13 : CAPCOM Channels Pin Assignement
CAPCOM Unit Channel 0 CC0 2.0 47 1 CC1 2.1 48 2 CC2 2.2 49 3 CC3 2.3 50 4 CC4 2.4 51 5 CC5 2.5 52 6 CC6 2.6 53 7 CC7 2.7 54 8 9 10 11 12 13 14 15
CAPCOM1 I/O Port Pin Number CAPCOM2 I/O Port Pin Number
CC81 CC91 CC101 CC111 CC12 CC13 CC14 CC15 2.8 57 2.9 58 2.10 59 CC26 1H.6 134 2.11 60 CC27 1H.7 135 2.12 61 2.13 62 2.14 63 2.15 64
CC16 CC17 CC18 CC19 CC20 CC21 CC22 CC23 CC24 CC25 8.0 9 8.1 10 8.2 11 8.3 12 8.4 13 8.5 14 8.6 15 8.7 16 1H.4 132 1H.5 133
CC28 CC29 CC30 CC31 7.4 23 7.5 24 7.6 25 7.7 26
Note: 1. Input only.
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10 - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer / counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2. Each timer in each module may operate independently in several different modes, or may be concatenated with another timer of the same module. 10.1 - GPT1 Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 14 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode. The count direction (up / down) for each timer is programmable by software or may be altered dynamically by an external signal on a port pin (TxEUD). In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be connected directly to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow / underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for high resolution of long duration measurements. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. 10.2 - GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture / reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up / down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6 which changes its state on each timer overflow / underflow.
Table 14 : GPT1 timer input frequencies, resolution and periods
Timer Input Selection T2I / T3I / T4I fCPU = 25MHz 000b Pre-scaler Factor Input Frequency Resolution Period 8 001b 16 010b 32 011b 64 390KHz 2.56s 167ms 100b 128 195.3KHz 5.12s 336ms 101b 256 97.66KHz 10.24s 671ms 110b 512 111b 1024
3.125MHz 1.563MHz 781.3MHz 320ns 21.0ms 640ns 41.9ms 1.28s 83.9ms
48.83KHz 24.41KHz 20.48s 1.34s 40.96s 2.68s
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The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The overflows / underflows of timer T6 can also be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register can capture the contents of T5 from an external signal transition on the corresponding port pin (CAPIN), and T5 may be optionally cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated on transitions of GPT1 timer T3 inputs T3IN and / or T3EUD. This is useful when T3 operates in Incremental Interface Mode. Table 15 GPT2 timer input frequencies, resolution and periods lists the timer input frequencies, resolution and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode.
Table 15 : GPT2 timer input frequencies, resolution and periods
Timer Input Selection T5I / T6I fCPU = 25MHz 000b Pre-scaler Factor Input Frequency Resolution Period 4 001b 8 010b 16 011b 32 100b 64 390KHz 2.56s 167ms 101b 128 110b 256 111b 512
6.25MHz 3.125MHz 1.563MHz 781.3KHz 160ns 10.49ms 320ns 21.0ms 640ns 41.9ms 1.28s 83.9ms
195.3KHz 97.66KHz 48.83KHz 5.12s 336ms 10.24s 671ms 20.48s 1.34s
Figure 6 : Block Diagram of GPT1
T2EUD
U/D GPT1 Timer T2
n
CPU Clock T2IN
2 n=3...10
Interrupt Request
T2 Mode Control
Reload Capture
CPU Clock
2n n=3...10
T3IN
T3 Mode Control
T3OUT GPT1 Timer T3 U/D Capture Reload T3OTL
T3EUD
T4IN CPU Clock
2n n=3...10
T4 Mode Control
Interrupt Request Interrupt Request
GPT1 Timer T4
T4EUD
U/D
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Figure 7 : Block Diagram of GPT2
T5EUD CPU Clock T5IN U/D 2n n=2...9
T5 Mode Control
GPT2 Timer T5 Clear Capture
Interrupt Request
CAPIN GPT2 CAPREL
Interrupt Request
Reload
Interrupt Request
T6IN CPU Clock T6EUD 2n n=2...9
T6 Mode Control
Toggle FF GPT2 Timer T6 U/D T60TL T6OUT to CAPCOM Timers
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11 - PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The Table 16 shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests.
Table 16 : PWM unit frequencies and resolution at 25MHz CPU clock
Mode 0 CPU Clock / 1 CPU Clock / 64 Mode 1 CPU Clock / 1 CPU Clock / 64 Resolution 40ns 2.56s Resolution 40ns 2.56s 8-bit 97.66KHz 1.526KHz 8-bit 48.82KHz 762.9Hz 10-bit 24.41KHz 381.5Hz 10-bit 12.20KHz 190.7Hz 12-bit 6.104KHz 95.37Hz 12-bit 3.05KHz 47.68Hz 14-bit 1.526KHz 23.84Hz 14-bit 762.9Hz 11.92Hz 16-bit 0.381Hz 5.96Hz 16-bit 190.7Hz 2.98Hz
Figure 8 : PWM Module Block Diagram
PPx Period Register *
Comparator
Match
Clock 1 Clock 2
Input Control
Run
* PTx 16-Bit Up/Down Counter
Up/Down/ Clear Control
Comparator
Match
Output Control Enable
POUTx
Shadow Register
Write Control
* User readable & writeable register
PWx Pulse Width Register *
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12 - PARALLEL PORTS The ST10F168 provides up to 111 I/O lines organized into eight input / output ports and one input port. All port lines are bit-addressable, and all input / output lines are individually (bit-wise) programmable as input or output via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push-pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS-like), where the special CMOS-like input threshold reduces noise sensitivity to the input hysteresis. The input thresholds are selected with bit of PICON register dedicated to blocks of 8 input pins (2-bit for Port2, 2-bit for Port3, 1-bit for Port7, 1-bit for Port8). All pins of I/O ports also support an alternate programmable function: - Port0 and Port1 may be used as address and data lines when accessing external memory. - Port 2, Port 7 and Port 8 are associated with the capture inputs or with the compare outputs of the CAPCOM units and / or with the outputs of the PWM module. - Port 3 includes the alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). - Port 4 outputs the additional segment address bit A16 to A23 in systems where segmentation is enabled to access more than 64K Byte of memory. - Port 5 is used as analog input channels of the A/D converter or as timer control signals. - Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. All port lines that are not used for alternate functions may be used as general purpose I/O lines.
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13 - A/D CONVERTER A10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. Overrun error detection / protection is controlled by the ADDAT register. Either an interrupt request is generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended until the previous result has been read. For applications which require less than 16 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the ST10F168 supports different conversion modes : - Single channel single conversion : the analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. - Single channel continuous conversion : the analog level of the selected channel is repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. - Auto scan single conversion : the analog level of the selected channels are sampled once and converted. After each conversion the result is stored in the ADDAT register. The data can be transfered to the RAM by interrupt software management or using the powerfull Peripheral Event Controller data transfert. - Auto scan continuous conversion : the analog level of the selected channels are repeatedly sampled and converted. The result of the conversion is stored in the ADDAT register. The data can be transfered to the RAM by interrupt software management or using the powerfull Peripheral Event Controller data transfert. - Wait for ADDAT read mode : when using continuous modes, in order to avoid to overwrite Table 17 : ADC sample clock and conversion clock
ADCTC 00 01 10 11 Conversion Clock tCC TCL1 = 1/2 x fXTAL TCL x 24 Reserved, do not use TCL x 96 TCL x 48 At fCPU = 25MHz 0.48s Reserved 1.92s 0.96s 00 01 10 11
the result of the current conversion by the next one, the ADWR bit of ADCON control register must be activated. Then, until the ADDAT register is read, the new result is stored in a temporary buffer and the conversion is on hold. - Channel injection mode : when using continuous modes, a selected channel can be converted in between without changing the current operating mode. The 10 bit data of the conversion are stored in ADRES field of ADDAT2. The current continuous mode remains active after the single conversion is completed. The Table 17 ADC sample clock and conversion clock shows conversion clock and sample clock of the ADC unit. A complete conversion will take 14tCC + 2tSC + 4TCL. This time includes the conversion it self, the sampling time and the time required to transfer the digital value to the result register. For example at 25MHz of CPU clock, the minimum complete conversion time is 7.76s. The A/D converter provides automatic offset and linearity self calibration. The calibration operation is performed in two ways : - A full calibration sequence is performed after a reset and lasts 1.25ms minimum (at 25MHz CPU clock). During this time, the ADBSY flag is set to indicate the operation. Normal conversion can be performed during this time. The duration of the calibration sequence is then extended by the time consumed by the conversions. Note : After a power-on reset, the total unadjusted error (TUE) of the ADC might be worse than 2LSB (max. 4LSB). During the full calibration sequence, the TUE is constantly improved until at the end of the cycle, TUE is within the specified limits of 2LSB. - One calibration cycle is performed after each conversion : each calibration cycle takes 4 ADC clock cycles. These operation cycles ensure constant updating of the ADC accuracy, compensating changing operating conditions.
ADSTC
Sample Clock tSC tSC = tCC tCC x 2 tCC x 4 tCC x 8 At fCPU = 25MHz 0.48s 2 0.96s 2 1.92s 2 3.84s 2
Notes: 1. See Section 20.5.5 - Direct Drive on page 55. 2. tCC = TCL x 24.
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14 - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASC0) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning. For transmission, reception and erroneous reception, 3 separate interrupt vectors are provided for each serial channel. ASC0 ASC0 supports full-duplex asynchronous communication at up to 781.25K Baud and half-duplex synchronous communication up to 5M Baud at 25MHz system clock. For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. Table 18 lists various commonly used Baud rates together with the required reload values and the deviation errors compared to the intended Baud rate. For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate.
Table 18 : Commonly used Baud rates by reload value and deviation errors
S0BRS = `0', fCPU = 25MHz Baud Rate (Baud) 781 250 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 95 Deviation Error 0.0% +7.3% / -0.4% +1.7% / -3.1% +1.7% / -0.8% +0.5% / -0.8% +0.5% / -0.1% +0.2% / -0.1% +0.0% / -0.1% +0.0% / -0.1% +0.4% Reload Value 0000h 000Ch / 000Dh 0013h / 0014h 0027h / 0028h 0050h/ 0051h 00A1h / 00A2h 0144h / 0145h 028Ah / 028Bh 0515h / 0516h 1FFFh / 1FFFh S0BRS = `1', fCPU = 25MHz Baud Rate (Baud) 520 833 56 000 38 400 19 200 9 600 4 800 2 400 1 200 600 75 63 Deviation Error 0.0% +3.3% / -7.0% +4.3% / -3.1% +0.5% / -3.1% +0.5% / -1.4% +0.5% / -0.5% +0.0% / -0.5% +0.0% / -0.2% +0.0% / -0.1% +0.0% / -0.0% +0.9% Reload Value 0000h 0008h / 0009h 000Ch / 000Dh 001Ah / 001Bh 0035h / 0036h 006Bh / 006Ch 00D8h / 00D9h 01B1h / 01B2h 0363h / 0364h 1B1Fh / 1B20h 1FFFh / 1FFFh
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High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial communication between the ST10F168 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit Baud rate generator provides the SSC with a separate serial clock signal. The serial channel SSC has its own dedicated 16-bit Baud rate generator with 16-bit reload capability, allowing Baud rate generation independent from the timers. SSCBR is the dual-function Baud rate Generator / Reload register. Table 19 lists some possible Baud rates against the required reload values and the resulting bit times for a 25MHz CPU clock. Note: The deviation errors given in the Table 18 are rounded. To avoid deviation errors use a Baud rate crystal (providing a multiple of the ASC0/SSC sampling frequency). Table 19 : Synchronous Baud rate and reload values
Baud Rate Reserved use a reload value > 0. 5M Baud 3.3M Baud 2.5M Baud 2M Baud 1M Baud 100K Baud 10K Baud 1K Baud 190.7 Baud Bit Time --200ns 303ns 400ns 500ns 1s 10s 100s 1ms 5.2ms Reload Value 0000h 0001h 0002h 0004h 0005h 000Bh 007Ch 04E1h 30D3h FFFFh
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15 - CAN MODULE The integrated CAN module completely handles the autonomous transmission and the reception of CAN frames according to the CAN specification V2.0 part B (active). The on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN Module Provides full CAN functionality on up to 15 message objects. Message object 15 can be configured for basic CAN functionality. Both modes provide separate masks for acceptance filtering, allowing a number of identifiers in full CAN mode to be accepted and disregarding a number of identifiers in basic CAN mode. All message objects can be updated independently from other objects and are equipped for the maximum message length of 8 Bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1M Baud. The CAN module uses two pins to interface to a bus transceiver. 16 - WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the
Reload value in WDTREL FFh 00h Prescaler for fCPU 2 (WDTIN = `0') 20.48s 5.24ms 128 (WDTIN = `1') 1.31ms 336ms
time interval until the EINIT (end of initialization) instruction has been executed. Therefore, the chip start-up procedure is always monitored. The software must be designed to service the watchdog timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is 16-bit, clocked with the system clock divided by 2 or 128. The high Byte of the watchdog timer register can be set to a pre-specified reload value (stored in WDTREL). Each time it is serviced by the application software, the high Byte of the watchdog timer is reloaded. For security, rewrite WDTCON each time before the watchdog timer is serviced. Table 20 shows the watchdog time range for 25MHz CPU clock. Table 20 : Watchdog time range (25MHz clock)
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17 - SYSTEM RESET Table 21 : Reset event definition
Reset Source Power-on reset Long Hardware reset (synchronous & asynchronous) Short Hardware reset (synchronous reset) Watchdog Timer reset Software reset Short-cut PONR LHWR SHWR WDTR SWR Power-on t RSTIN > 1032 TCL 4 TCL < t RSTIN < 1032 TCL WDT overflow SRST execution Conditions
System reset initializes the MCU in a predefined state. There are five ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 21. 17.1 - Asynchronous Reset (Long Hardware Reset) An asynchronous reset is triggered when RSTIN pin is pulled low while VPP pin is at low level. Then the MCU is immediately forced in reset default state. It pulls low RSTOUT pin, it cancels pending internal hold states if any, it waits for any internal access cycles to finish, it aborts external bus cycle, it switches buses (data, address and control signals) and I/O pin drivers to high-impedance, it pulls high Port0 pins and the reset sequence starts. Power-on Reset The asynchronous reset must be used during the power-on of the MCU. Depending on crystal frequency, the on-chip oscillator needs about 10ms to 50ms to stabilize. The logic of the MCU does not need a stabilized clock signal to detect an asynchronous reset, so it is suitable for power-on Figure 9 : Asynchronous Reset Timing
6 or 8 TCL1 CPU Clock RSTIN Asynchronous Reset Condition VPP RSTOUT ALE
conditions. To ensure a proper reset sequence, the RSTIN pin and the VPP pin must be held at low level until the MCU clock signal is stabilized and the system configuration value on Port0 is settled. Hardware Reset The asynchronous reset must be used to recover from catastrophic situations of the application. It may be triggerred by the hardware of the application. Internal hardware logic and application circuitry are described in Reset circuitry chapter and Figures 12, 13 and 14. Exit of Asynchrounous Reset State When the RSTIN pin is pulled high, the MCU restarts. The system configuration is latched from Port0 and ALE, RD and R/W pins are driven to their inactive level. The MCU starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of asynchronous reset sequence are summarized in Figure 9.
Port0 Internal Reset Signal
Reset Configuration Latching point of Port0 for system start-up configuration
INST #1
Note: 1. RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL).
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17.2 - Synchronous Reset (Warm Reset) A synchronous reset is triggered when RSTIN pin is pulled low while VPP pin is at high level. In order to properly activate the internal reset logic of the MCU, the RSTIN pin must be held low, at least, during 4 TCL (2 periods of CPU clock). The I/O pins are set to high impedance and RSTOUT pin is driven low. After RSTIN level is detected, a short duration of 12 TCL (approximately 6 periods of CPU clock) elapes, during which pending internal hold states are cancelled and the current internal access cycle if any is completed. External bus cycle is aborted. The internal pulldown of RSTIN pin is activated if bit BDRSTEN of SYSCON register was previously set by software. This bit is always cleared on power-on or after a reset sequence. Exit of Synchrounous Reset State The internal reset sequence starts for 1024 TCL (512 periods of CPU clock) and RSTIN pin level is sampled. The reset sequence is extended until RSTIN level becomes high. Then, the MCU restarts. The system configuration is latched from Port0 and ALE, RD and R/W pins are driven to their inactive level. The MCU starts program execution from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine. Timing of synchronous reset sequence are summarized in Figure 10 and 11.
Figure 10 : Synchronous Warm Reset: Short low pulse on RSTIN
4 TCL min. 12 TCL max. 1024 TCL 6 or 8 TCL3
CPU Clock
RSTIN VPP
1
Internally pulled low4
200A Discharge
2
VPP > 2.5V Asynchronous Reset not entered.
RSTOUT ALE
Port0
Reset Configuration Latching point of Port0 for system start-up configuration
INST #1
Internal Reset Signal
Notes: 1. RSTIN assertion can be released there. 2. If during the reset condition (RSTIN low), Vpp voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL). 4) RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SUSCON register) was previously set by software. Bit BDRSTEN is cleared after reset.
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Figure 11 : Synchronous Warm Reset: Long low pulse on RSTIN
4 TCL 12 TCL 1024 TCL 6 or 8 TCL1
CPU Clock
RSTIN VPP
Internally pulled low3
200A Discharge
2
VPP > 2.5V Asynchronous Reset not entered.
RSTOUT ALE
Port0
Reset Configuration Latching point of Port0 for system start-up configuration
Internal Reset Signal
Notes: 1. RSTIN rising edge to internal latch of Port0 is 3CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (fCPU = fXTAL / 2), else it is 4 CPU clock cycles (8 TCL). 2. If during the reset condition (RSTIN low), Vpp voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by soft-ware. Bit BDRSTEN is cleared after reset.
READY is sampled active (low) after the programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence is started. Bit P0.12...P0.8 are latched at the end of the reset sequence and bit P0.7...P0.2 are cleared. 17.5 - Reset Circuitry Internal reset circuitry is described in Figure 13. The RSTIN pin provides an internal pullup resistor of 50K to 250K (The minimum reset time must be calculated using the lowest value). It also provides a programmable (BDRSTEN bit of SYSCON register) pulldown to output internal reset state signal (synchronous reset, watchdog timer reset or software reset). This bidirectional reset function is useful in applications where external devices require a reset signal but cannot be connected to RSTOUT pin. This is the case of an external memory running codes before EINIT ( end of initialization) instruction is executed. RSTOUT pin is pulled high only when EINIT is executed. The VPP pin provides an internal weak pulldown resistor which discharges external capacitor at a typical rate of 200A. If bit PWDCFG of SYSCON register is set, an internal pullup resistor is activated at the end of the reset sequence. This pullup will charge any capacitor connected on VPP pin.
17.3 - Software Reset A software reset sequence can be triggered at any time by the protected SRST (software reset) instruction. This instruction can be deliberately executed within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals system failure. On execution of the SRST instruction, the internal reset sequence is started. The microcontroller behaviour is the same as for a synchronous reset, except that only bit P0.12...P0.8 are latched at the end of the reset sequence, while previously latched, bit P0.7...P0.2 are cleared. 17.4 - Watchdog Timer Reset When the watchdog timer is not disabled during the initialization, or serviced regularly during program execution, it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY, or if
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The simplest way to reset the ST10F168 is to insert a capacitor C1 between RSTIN pin and VSS, and a capacitor between VPP pin and VSS (C0) with a pullup resistor R0 between VPP pin and VCC. The input RSTIN provides an internal pullup device equalling a resistor of 50k to 150k (the minimum reset time must be determined by the lowest value). Select C1 that produce a sufficient discharge time to permit the internal or external oscillator and / or internal PLL to stabilize. To insure correct power-up reset with controlled supply current consumption, specially if clock signal requires a long period of time to stabilized, an asynchronous hardware reset is required during power-up. It is recommended to connect the external R0C0 circuit shown in Figure 12 to the VPP pin. On power-up, the logical low level on VPP pin forces an asynchronous harware reset when RSTIN is asserted. The external pullup R0 will then charge the capacitor C0. Note that an internal pulldown device on VPP pin is turned on when RSTIN pin is low, and causes the external capacitor (C0) to begin discharging at a typical rate of 100A to 200A. With this mechanism, after power-up reset, short low pulses applied on RSTIN produce synchronous hardware reset. If RSTIN is asserted longer than Figure 13 : Internal (simplified) Reset Circuitry
EINIT Instruction Clr Q Set RSTOUT
the time needed for C0 to be discharged by the internal pulldown device, then the device is forced in an asynchronous reset. This mechanism insures recovery from very catastrophic failure. Figure 12 : Minimum External Reset Circuitry
RSTOUT RSTIN
External Hardware + C1 a) Hardware Reset
VCC
R0 VPP + C0 ST10F168
b) For Power-up Reset (and Interruptible Power-down mode)
Reset State Machine Clock
VCC
Internal Reset Signal
Trigger Clr
SRST instruction watchdog overflow
RSTIN
BDRSTEN Reset Sequence (512 CPU Clock Cycles)
VCC Asynchronous Reset
VPP (Flash device) From/to Exit Powerdown Circuit
VPP
Weak Pulldown (~200A)
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The minimum reset circuit of Figure 14 is not adequate when the RSTIN pin is driven from the ST10F168 itself during software or watchdog triggered resets, because of the capacitor C1 that will keep the voltage on RSTIN pin above VIL after the end of the internal reset sequence, and thus will triggered an asynchronous reset sequence. Figure 14 shows an example of a reset circuit. In this example, R1C1 external circuit is only used to Figure 14 : System Reset Circuit
VCC VCC R2 RSTOUT
generate power-up or manual reset, and R0C0 circuit on VPP is used for power-up reset and to exit from powerdown mode. Diode D1 creates a wired-OR gate connection to the reset pin and may be replaced by open-collector schmitt trigger buffer. Diode D2 provides a faster cycle time for repetitive power-on resets. R2 is an optional pullup for faster recovery and correct biasing of TTL Open Collector drivers.
External Hardware D2 R1
RSTIN VCC D1 o.d. R0 Open Drain Inverter VPP + C0 ST10F168 External Reset Source
+ C1
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ST10F168
18 - POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can be configured by software in order to be terminated only by a hardware reset or by an external interrupt source on fast external interrupt pins. There are two different operating Power Down modes: - Protected power down mode: selected by setting bit PWDCFG in the SYSCON register to `0'. This mode can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent. The microcontroller enters the NMI trap routine and saves the internal state into RAM. The trap routine then sets a flag or writes a bit pattern into specific RAM locations, and executes the PWRDN instruction. If the NMI pin is still low at this time, Power Down mode will be entered, if not program execution continues. During power down the voltage at the VCC pins can be lowered to 2.5 V and the contents of the internal RAM will still be preserved. - Interruptible power down mode: this mode is selected by setting bit PWDCFG in the SYSCON register. The CPU and peripheral clocks are frozen, and the oscillator and PLL are stopped. To exit power down mode with an external interrupt, an EXxIN (x = 7...0) pin has to be asserted for at least 40ns. This signal enables the internal oscillator and PLL circuitry, and turns on the weak pulldown. If the Interrupt was enabled before entering power down mode, the device executes the interrupt service routine, and then resumes execution after the PWRDN instruction. If the interrupt was disabled, the device executes the instruction following PWRDN instruction, and the Interrupt Request Flag remains set until it is cleared by software. All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access.
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ST10F168
19 - SPECIAL FUNCTION REGISTER OVERVIEW Table 22 lists all SFRs which are implemented in the ST10F168 in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Table 22 : Special Function Registers listed by name
Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC BUSCON0 BUSCON1 BUSCON2 BUSCON3 BUSCON4 CAPREL CC0 CC0IC CC1 CC1IC CC2 CC2IC CC3 CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8 CC8IC CC9 b b b b b b b b b b b b b b b b b Physical address FF98h FFA0h FEA0h F0A0h FE18h FE1Ah FE1Ch FE1Eh FF9Ah FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah FE80h FF78h FE82h FF7Ah FE84h FF7Ch FE86h FF7Eh FE88h FF80h FE8Ah FF82h FE8Ch FF84h FE8Eh FF86h FE90h FF88h FE92h E 8-bit address CCh D0h 50h 50h 0Ch 0Dh 0Eh 0Fh CDh 86h 8Ah 8Bh 8Ch 8Dh 25h 40h BCh 41h BDh 42h BEh 43h BFh 44h C0h 45h C1h 46h C2h 47h C3h 48h C4h 49h Description A/D Converter End Of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D converter Overrun Error Interrupt Control Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture / Reload Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Control Register CAPCOM Register 1 CAPCOM Register 1 Interrupt Control Register CAPCOM Register 2 CAPCOM Register 2 Interrupt Control Register CAPCOM Register 3 CAPCOM Register 3 Interrupt Control Register CAPCOM Register 4 CAPCOM Register 4 Interrupt Control Register CAPCOM Register 5 CAPCOM Register 5 Interrupt Control Register CAPCOM Register 6 CAPCOM Register 6 Interrupt Control Register CAPCOM Register 7 CAPCOM Register 7 Interrupt Control Register CAPCOM Register 8 CAPCOM Register 8 Interrupt Control Register CAPCOM Register 9 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0XX0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 43/74
An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers).
ST10F168
Table 22 : Special Function Registers listed by name
Name CC9IC CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC28 CC28IC CC29 44/74 b b b b b b b b b b b b b b b b b b b b Physical address FF8Ah FE94h FF8Ch FE96h FF8Eh FE98h FF90h FE9Ah FF92h FE9Ch FF94h FE9Eh FF96h FE60h F160h FE62h F162h FE64h F164h FE66h F166h FE68h F168h FE6Ah F16Ah FE6Ch F16Ch FE6Eh F16Eh FE70h F170h FE72h F172h FE74h F174h FE76h F176h FE78h F178h FE7Ah E E E E E E E E E E E E E 8-bit address C5h 4Ah C6h 4Bh C7h 4Ch C8h 4Dh C9h 4Eh CAh 4Fh CBh 30h B0h 31h B1h 32h B2h 33h B3h 34h B4h 35h B5h 36h B6h 37h B7h 38h B8h 39h B9h 3Ah BAh 3Bh BBh 3Ch BCh 3Dh Description CAPCOM Register 9 Interrupt Control Register CAPCOM Register 10 CAPCOM Register 10 Interrupt Control Register CAPCOM Register 11 CAPCOM Register 11 Interrupt Control Register CAPCOM Register 12 CAPCOM Register 12 Interrupt Control Register CAPCOM Register 13 CAPCOM Register 13 Interrupt Control Register CAPCOM Register 14 CAPCOM Register 14 Interrupt Control Register CAPCOM Register 15 CAPCOM Register 15 Interrupt Control Register CAPCOM Register 16 CAPCOM Register 16 Interrupt Control Register CAPCOM Register 17 CAPCOM Register 17 Interrupt Control Register CAPCOM Register 18 CAPCOM Register 18 Interrupt Control Register CAPCOM Register 19 CAPCOM Register 19 Interrupt Control Register CAPCOM Register 20 CAPCOM Register 20 Interrupt Control Register CAPCOM Register 21 CAPCOM Register 21 Interrupt Control Register CAPCOM Register 22 CAPCOM Register 22 Interrupt Control Register CAPCOM Register 23 CAPCOM Register 23 Interrupt Control Register CAPCOM Register 24 CAPCOM Register 24 Interrupt Control Register CAPCOM Register 25 CAPCOM Register 25 Interrupt Control Register CAPCOM Register 26 CAPCOM Register 26 Interrupt Control Register CAPCOM Register 27 CAPCOM Register 27 Interrupt Control Register CAPCOM Register 28 CAPCOM Register 28 Interrupt Control Register CAPCOM Register 29 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
ST10F168
Table 22 : Special Function Registers listed by name
Name CC29IC CC30 CC30IC CC31 CC31IC CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 CP CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DP7 DP8 DPP0 DPP1 DPP2 DPP3 EXICON IDCHIP IDMANUF IDMEM IDPROG MDC MDH MDL ODP2 ODP3 b b b b b b b b b b b b b b b b b b b b b b b b b b Physical address F184h FE7Ch F18Ch FE7Eh F194h FF52h FF54h FF56h FF58h FF22h FF24h FF26h FF28h FE10h FF6Ah FE08h F100h F102h F104h F106h FFC2h FFC6h FFCAh FFCEh FFD2h FFD6h FE00h FE02h FE04h FE06h F1C0h F07Ch F07Eh F07Ah F078h FF0Eh FE0Ch FE0Eh F1C2h F1C6h E E E E E E E E E E E E E E 8-bit address C2h 3Eh C6h 3Fh CAh A9h AAh ABh ACh 91h 92h 93h 94h 08h B5h 04h 80h 81h 82h 83h E1h E3h E5h E7h E9h EBh 00h 01h 02h 03h E0h 3Eh 3Fh 3Dh 3Ch 87h 06h 07h E1h E3h Description CAPCOM Register 29 Interrupt Control Register CAPCOM Register 30 CAPCOM Register 30 Interrupt Control Register CAPCOM Register 31 CAPCOM Register 31 Interrupt Control Register CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register P0h Direction Control Register P1L Direction Control Register P1h Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Register (10-bit) CPU Data Page Pointer 1 Register (10-bit) CPU Data Page Pointer 2 Register (10-bit) CPU Data Page Pointer 3 Register (10-bit) External Interrupt Control Register Device Identifier Register Manufacturer Identifier Register On-chip Memory Identifier Register Programming Voltage Identifier Register CPU Multiply Divide Control Register CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FC00h 0000h 0000h 00h 00h 00h 00h 0000h 0000h 00h 00h 00h 00h 0000h 0001h 0002h 0003h 0000h 0A8Xh1 0400h 3040h 9A40h 0000h 0000h 0000h 0000h 0000h 45/74
ST10F168
Table 22 : Special Function Registers listed by name
Name ODP6 ODP7 ODP8 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 P7 P8 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON PP0 PP1 PP2 PP3 PSW PT0 PT1 PT2 PT3 PW0 PW1 PW2 PW3 PWMCON0 b PWMCON1 b b b b b b b b b b b b b b b b b Physical address F1CEh F1D2h F1D6h FF1Eh FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h FFCCh FFD0h FFD4h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh F1C4h F038h F03Ah F03Ch F03Eh FF10h F030h F032h F034h F036h FE30h FE32h FE34h FE36h FF30h FF32h E E E E E E E E E E E E 8-bit address E7h E9h EBh 8Fh 80h 81h 82h 83h E0h E2h E4h D1h E6h E8h EAh 60h 61h 62h 63h 64h 65h 66h 67h E2h 1Ch 1Dh 1Eh 1Fh 88h 18h 19h 1Ah 1Bh 18h 19h 1Ah 1Bh 98h 99h Description Port 6 Open Drain Control Register Port 7 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of Port0) Port 0 High Register (Upper half of Port0) Port 1 Low Register (Lower half of Port1) Port 1 High Register (Upper half of Port1) Port 2 Register Port 3 Register Port 4 Register (8-bit) Port 5 Register (read only) Port 6 Register (8-bit) Port 7 Register (8-bit) Port 8 Register (8-bit) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register PWM Module Period Register 0 PWM Module Period Register 1 PWM Module Period Register 2 PWM Module Period Register 3 CPU Program Status Word PWM Module Up / Down Counter 0 PWM Module Up / Down Counter 1 PWM Module Up / Down Counter 2 PWM Module Up / Down Counter 3 PWM Module Pulse Width Register 0 PWM Module Pulse Width Register 1 PWM Module Pulse Width Register 2 PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 Reset value 00h 00h 00h FFFFh 00h 00h 00h 00h 0000h 0000h 00h XXXXh 00h 00h 00h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
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ST10F168
Table 22 : Special Function Registers listed by name
Name PWMIC RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON T0 T01CON T0IC T0REL T1 T1IC T1REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC b b b b b b b b b b b b b b b b b b b b b b b Physical address F17Eh F108h FEB4h FFB0h FF70h FEB2h FF6Eh F19Ch FEB0h FF6Ch FE12h F0B4h FFB2h FF76h F0B2h FF74h F0B0h FF72h FE14h FE16h FF12h FE50h FF50h FF9Ch FE54h FE52h FF9Eh FE56h FE40h FF40h FF60h FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h E E E E E E 8-bit address BFh 84h 5Ah D8h B8h 59h B7h CEh 58h B6h 09h 5Ah D9h BBh 59h BAh 58h B9h 0Ah 0Bh 89h 28h A8h CEh 2Ah 29h CFh 2Bh 20h A0h B0h 21h A1h B1h 22h A2h B2h 23h A3h B3h Description PWM Module Interrupt Control Register System Start-up Configuration Register (read only) Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Register (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baud Rate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Control Register CAPCOM Timer 0 Interrupt Control Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Interrupt Control Register CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register Reset value 0000h XXh 0000h 0000h 0000h XXh 0000h 0000h 00h 0000h FC00h 0000h 0000h 0000h XXXXh 0000h 0000h 0000h FA00h FC00h 0xx0h2 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 47/74
ST10F168
Table 22 : Special Function Registers listed by name
Name T6 T6CON T6IC T7 T78CON T7IC T7REL T8 T8IC T8REL TFR WDT WDTCON XP0IC XP1IC XP2IC XP3IC ZEROS b b b b b b b b b b b b Physical address FE48h FF48h FF68h F050h FF20h F17Ah F054h F052h F17Ch F056h FFACh FEAEh FFAEh F186h F18Eh F196h F19Eh FF1Ch E E E E E E E E E E 8-bit address 24h A4h B4h 28h 90h BEh 2Ah 29h BFh 2Bh D6h 57h D7h C3h C7h CBh CFh 8Eh GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Control Register CAPCOM Timer 7 Interrupt Control Register CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Control Register CAPCOM Timer 8 Reload Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register CAN Module Interrupt Control Register X-Peripheral 1 Interrupt Control Register X-Peripheral 2 Interrupt Control Register PLL unlock Interrupt Control Register Constant Value 0's Register (read only) Description Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 000xh3 0000h4 0000h4 0000h4 0000h4 0000h
Notes: 1. The value depends on the silicon revision and is described in the chapter 19.1. 2. The system configuration is selected during reset. 3. Bit WDTR indicates a watchdog timer triggered reset. 4. The XPnIC Interrupt Control Registers control the interrupt requests from integrated X-Bus peripherals. Nodes where no X-Peripherals are connected may be used to generate software controlled interrupt requests by setting the respective XPnIR bit.
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ST10F168
19.1 - Identification Registers The ST10F168 has four Identification registers, mapped in ESFR space. These register contain: - - - - A manufacturer identifier, A chip identifier, with its revision, A internal memory and size identifier, Programming voltage description. ESFR
11 10 MANUF R 9 8 7 6 5 4
-
IDMANUF (F07Eh / 3Fh)
15 14 13 12
3
-
2
-
1
-
0
-
Description
MANUF : Manufacturer Identifier - 020h: STmicroelectronics Manufacturer (JTAG worldwide normalisation). IDCHIP (F07Ch / 3Eh)
15 14 13 12 11 10 CHIPID R 9
ESFR
8 7 6 5 4 3 2 REVID R 1 0
Description
REVID : CHIPID : Device Revision Identifier - 1h for the first step, 2h for the second step,... Device Identifier - 0A8h is the identifier of ST10F168. ESFR
12 11 10 9 8 7 6 MEMSIZE R 5 4 3 2 1 0
IDMEM (F07Ah / 3Dh)
15 14 MEMTYP R 13
Description
MEMSIZE : MEMTYP : Internal Memory Size - 040h for ST10F168 (256K Bytes). Internal Memory size is 4 * (in K Byte). Internal Memory Type - 3h for ST10F168 (Flash memory). ESFR
11 10 9 8 7 6 5 4 PROGVDD R 3 2 1 0
IDPROG (F078h / 3Ch)
15 14 13 12 PROGVPP R
Description
PROGVDD : Programming VDD Voltage VDD voltage when programming EPROM or Flash devices is calculated using the following formula: VDD = 20 * / 256 [V] - 40h for ST10F168 (5V). Programming VPP Voltage VPP voltage when programming EPROM or Flash devices is calculated using the following formula: VPP = 20 * / 256 [V] - 9Ah for ST10F168 (12V).
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PROGVPP :
ST10F168
20 - ELECTRICAL CHARACTERISTICS 20.1 - Absolute Maximum Ratings
Symbol VDD VIO IOV ITOV Ptot TA Tstg Parameter Voltage on VDD pins with respect to ground1 Voltage on any pin with respect to ground Input Current on any pin during overload
1
Value -0.5, +6.5 -0.5, (VDD +0.5) -10, +10
1
Unit V V mA mA W C C C
condition1
Absolute Sum of all input currents during overload condition Power Dissipation
1
|100 mA| 1.5
Ambient Temperature under bias for Ambient Temperature under bias for Storage Temperature1
Q61 Q31
-40, +85 -40, +125 -65, +150
Note: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN20.2 - Parameter Interpretation The parameters listed in the following tables represent the characteristics of the ST10F168 and its demands on the system. Where the ST10F168 logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the "Symbol" column. Where the external system must provide signals with their respective timing characteristics to the ST10F168, the symbol "SR" for System Requirement is included in the "Symbol" column. 20.3 - DC Characteristics VDD = 5V 10%, VSS = 0V, Reset active, for Q6 version : TA = -40, +85C and for Q3 version TA = -40, +125C, unless otherwise specified.
Symbol VIL VILS VIH VIH1 VIH2 VIHS HYS VOL VOL1 VOH VOH1 IOZ1 50/74 CC SR Input low voltage SR Input low voltage (special threshold) SR Input high voltage (all except RSTIN and XTAL1) Parameter Test Conditions - - - - - - - Min. - 0.5 - 0.5 0.2 VDD + 0.9 0.6 VDD 0.7 VDD 0.8 VDD - 0.2 300 - - 0.9 VDD 2.4 0.9 VDD 2.4 - Max. 0.2 VDD - 0.1 2.0 VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 0.45 0.45 - - - - 0.5 Unit V V V V V V mV V V V V V A
SR Input high voltage RSTIN SR Input high voltage XTAL1 SR Input high voltage (special threshold) Input Hysteresis (special threshold) voltage 1 (Port0,
Port1, Port 4, ALE, Output low IOL = 2.4mA RD, WR, BHE, CLKOUT, RSTOUT) IOL1 = 1.6mA
CC Output low voltage1 (all other outputs) CC
Output high voltage1 (Port0, Port1, Port4, ALE, IOH = - 500A RD, WR, BHE, CLKOUT, RSTOUT) IOH = -2.4mA IOH = - 250A IOH = - 1.6mA 0V < VIN < VDD
CC Output high voltage 1 2 (all other outputs) CC Input leakage current (Port 5)
ST10F168
Symbol IOZ2 IOV RRST IRWH IRWL IALEL IALEH IP6H IP6L IP0H IP0L IIL CIO ICC IID IPD IPPR IPPW VPP11
5 7 6 6 6 7 6 7
Parameter
Test Conditions 0V < VIN < VDD
34
Min. - - 50 - -500 40 - - -500 - -100 - - - - - - - 11,4
Max. 1 5 250 -40 - - 600 -40 - -10 - 20 10 20 + 6 x fCPU 20 + 3 x fCPU 100 200 20 12,6
Unit A mA k A A A A A A A A A pF mA mA A A mA V
CC Input leakage current (all other) SR Overload current CC RSTIN pull-up resistor 3 Read / Write inactive current Read / Write active current ALE inactive current ALE active current
6 6 6 6 6
0V < VIN < VILmax VOUT = 2.4V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4V VOUT = 2.4V VOUT = VOL1max VIN = VIHmin VIN = VILmax
Port 6 inactive current Port 6 active current
6
Port 0 configuration current 6 CC XTAL1 input current CC Pin capacitance 6 (digital inputs / outputs) Power supply current Idle mode supply current Power-down mode supply current VPP Read Current VPP Programming / Erasing Current 3 VPP during Programming / Erasing Operations
0V < VIN < VDD f = 1MHz, TA = 25C RSTIN = VIH1 fCPU in [MHz] 8 RSTIN = VIH1 fCPU in [MHz] 9 VDD = 5.5V 10 VPP < VDD VPP = 12V, fCPU = 25MHz
Notes: 1. ST10F168 pins are equipped with low-noise output drivers which significantly improve the device's EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached. After this, the output current is reduced. This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column "Test Conditions" is delivered in all cases. 2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 3. Partially tested, guaranteed by design characterization. 4. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD+0.5V or VOV < -0.5V). The absolute sum of input overload currents on all port pins may not exceed 50mA. The supply voltage must remain within the specified limits. 5. The maximum current may be drawn while the respective signal line remains inactive. 6. This specification is only valid during Reset, or during Hold-mode or Adapt-mode. Port 6 pins are only affected if they are used for CS output and the open drain function is not enabled. 7. The minimum current must be drawn in order to drive the respective signal line active. 8. The power supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These parameters are tested at VDDmax and 25MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. The chip is configured with a demultiplexed 16-bit bus, direct clock drive, 5 chip select lines and 2 segment address lines, EA pin is low during reset. After reset, Port 0 is driven with the value `00CCh' that produces infinite execution of NOP instruction with 15 wait-state, R/W delay, memory tristate wait state, normal ALE. Peripherals are not activated. 9. Idle mode supply current is a function of the operating frequency. This dependency is illustrated in the Figure 15. These parameters are tested at VDDmax and 25MHz CPU clock with all outputs disconnected and all inputs at VIL or VIH. 10. This parameter value includes leakage currents. With all inputs (including pins configured as inputs) at 0 V to 0.1V or at VDD - 0.1V to VDD, VREF = 0V, all outputs (including pins configured as outputs) disconnected. 11. Apply 12V on VPP 10ms after VDD is stable at power up. VPP pin must be switched to 0V before to switch off VDD (5V).
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ST10F168
Figure 15 : Supply / idle current as a function of operation frequency
I [mA]
100
10
20.4 - A/D Converter Characteristics VDD = 5V 10%, VSS = 0V, 4.0V VAREF VDD + 0.1V, VSS - 0.1V VAGND VSS + 0.2V, Q6 version : TA = -40, +85C and for Q3 version TA = -40C, +125C, unless otherwise specified
Symbol VAIN tS tC TUE Parameter Test Conditions
1-8 2-4 3-4 5
SR Analog input voltage range CC Sample time CC Conversion time CC Total unadjusted error
RAREF SR Internal resistance of reference voltage source RASRC SR Internal resistance of analog source CAIN CC ADC input capacitance
Notes: 1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000h or X3FFh, respectively. 2. During the tS sample time the input capacitance Cain can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within the tS sample time. After the end of the tS sample time, changes of the analog input voltage have no effect on the conversion result. Values for the tSC sample clock depend on the programming. Referring to the tC conversion time formula of chapter 13, to the table 17 of page 33 and to the table below: tS min = 2 tSC min = 2 tCC min = 2 x 24 x TCL = 48 TCL tS max = 2 tSC max = 2 x 8 tCC max = 2 x 8 x 96 TCL = 1536 TCL TCL is defined in section 20.5.5 at page 55. 3. The conversion time formula is: tC = 14 tCC + tS + 4 TCL (= 14 tCC + 2 tSC + 4 TCL) The tC parameter includes the tS sample time, the time for determining the digital result and the time to load the result register with the result of the conversion. Values for the tCC conversion clock depend on the programming. Referring to the table 17 of page 33 and to the table below: tC min = 14 tCC min + tS min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL tC max = 14 tCC max + tS max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL 4. This parameter is fixed by ADC control logic. 5. TUE is tested at VAREF = 5.0V, VAGND = 0V, VCC = 4.9V. It is guaranteed by design characterization for all other voltages within the defined voltage range. The specified TUE is guaranteed only if an overload condition (see Iov specification) occurs on maximum of 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA. During the reset calibration sequence the maximum TUE may be 4 LSB.
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000 0 00 00 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
ICCmax IIDmax 5 10 15 20
200
25
fCPU [MHz]
Min. VAGND 48 TCL 388 TCL -
Max. VAREF 1 536 TCL 2 884 TCL 2 (tCC / 165) - 0.25 (tS / 330) - 0.25 33
Unit V
LSB k k pF
tCC in [ns] tS in [ns]
7
6-7 2-7
- - -
ST10F168
6. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within tCC. The maximum internal resistance results from the programmed conversion timing. 7. Partially tested, guaranteed by design characterization. 8. To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at the ADC input. The cut-off frequency of this filter must be twice the highest conversion frequency used in the application as described in the formula: fcut-off = 2 / tc app where tc app is the shorter conversion time used in the application, calculated with the following formula: tc app = 14 tCC + tS + 4 TCL (= 14 tCC + 2 tSC + 4 TCL).
ADC Sample time and conversion time are programmable. The table below should be used to calculate the above timings.
Conversion Time ADCON.15|14 (ADCTC) 00 01 10 11 Conversion clock tCC TCL x 24 Reserved, do not use TCL x 96 TCL x 48 Sample Time ADCON.13|12 (ADSTC) 00 01 10 11 Sample clock tSC tCC tCC x 2 tCC x 4 tCC x 8
20.5 - AC Characteristics 20.5.1 - Test Waveforms Figure 16 : Input / output waveforms
2.4V 0.2VDD+0.9 Test Points 0.2VDD+0.9
0.45V
0.2VDD-0.1
0.2VDD-0.1
AC inputs during testing are driven at 2.4V for a logic `1' and 0.4V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'. Figure 17 : Float waveforms
VOH VOH -0.1V Timing Reference Points VOL +0.1V VOL
VLoad +0.1V VLoad VLoad -0.1V
For timing purposes a port pin is no longer floating when VLOAD changes of 100mV. It begins to float when a 100mV change from the loaded VOH/VOL level occurs (I OH/IOL = 20mA).
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ST10F168
20.5.2 - Definition of Internal Timing The internal operation of the ST10F168 is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see Figure 18). The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F168. The example for PLL operation shown in the Figure 18 refers to a PLL factor of 4. The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5).
Figure 18 : Generation Mechanisms for the CPU Clock
Phase locked loop operation fXTAL fCPU Direct Clock Drive fXTAL
Prescaler Operation fXTAL fCPU
TCL
TCL
20.5.3 - Clock Generation Modes The Table 23 associates the combinations of these three bit with the respective clock generation mode. Table 23 : CPU Frequency Generation
P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 fXTAL x 4 fXTAL x 3 fXTAL x 2 fXTAL x 5 fXTAL x 1 fXTAL x 1.5 fXTAL / 2 fXTAL x 2.5 2.5 to 6.25MHz 3.33 to 8.33MHz 5 to 12.5MHz 2 to 5MHz 1 to 25MHz 6.66 to 16.6MHz 2 to 50MHz 4 to 10MHz CPU clock via prescaler 3 Direct drive 2 Notes Default configuration
Notes: 1. The external clock input range refers to a CPU clock range of 1...25MHz. 2. The maximum depends on the duty cycle of the external clock signal. 3. The maximum input frequency is 25MHz when using an external crystal with the internal oscillator; providing that internal serial resistance of the crystal is less than 40. However, higher frequencies can be applied with an external clock source on pin XTAL1, but in this case, the input clock signal must reach the defined levels VIL and VIH2.
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000000 000000 000
TCL TCL
fCPU
00000000 00000000 0000
TCL TCL
00 000000
0 000
0 000
ST10F168
20.5.4 - Prescaler Operation When pins P0.15-13 (P0H.7-5) equal '001' during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. The timings listed in the AC Characteristics that refer to TCL therefore can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. 20.5.5 - Direct Drive When pins P0.15-13 (P0H.7-5) equal '011' during reset the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. Therefore, the timings given in this chapter refer to the minimum TCL. This minimum value can be calculated by the following formula: TCL min = 1 f XTAL x DC min DC = duty cycle For two consecutive TCLs, the deviation caused by the duty cycle of fXTAL is compensated, so the duration of 2TCL is always 1/fXTAL. The minimum value TCLmin has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL = 1 f XTAL Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fXTAL x DCmax) instead of TCLmin. 20.5.6 - Oscillator Watchdog (OWD) When the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the PLL circuitry. This oscillator watchdog operates as follows : After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, the bit OWDDIS (bit 4 of SYSCON register) must be set. When the OWD is enabled, the PLL runs on its free-running frequency, and increments the Oscillator Watchdog counter. On each transition of XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current. 20.5.7 - Phase Locked Loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock (see Table 23). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL x F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCL. The timings listed in the AC Characteristics that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances.
If bit OWDDIS in the SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off.
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ST10F168
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is refered to one TCL period. It decreases according to the formula and to the Figure 19 given below. For N periods of TCL the minimum value is computed using the corresponding deviation DN:
TCL MIN = TCL

DN x 1 - ------------NOM 100

D = ( 4 - N 15 ) [ % ] N
where N = number of consecutive TCL periods and 1 N 40. So for a period of 3 TCL periods (N = 3): D3 = 4 - 3/15 = 3.8% 3TCLmin = 3TCLNOM x (1 - 3.8/100) = 3TCLNOM x 0.962 3TCLmin = (57.72ns at fCPU = 25MHz) This is especially important for bus cycles using wait states and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is negligible (see Figure 19).
Figure 19 : Approximated maximum PLL jitter
Max.jitter [%] This approximated formula is valid for 1 < N < 40 and 10MHz < fCPU < 25MHz.
4 3 2 1
2 4 8 16
32
N
20.5.8 - External Clock Drive XTAL1 VDD = 5V 10%, VSS = 0V, for Q6 version : TA = -40, +85C and for Q3 version TA = -40, + 125C, unless otherwise specified.
fCPU = fXTAL Symbol Parameter Min. tOSC t1 t2 t3 t4 SR SR SR SR SR Oscillator period High time Low time Rise time Fall time 40 1 18 18 - -
2 2
fCPU = fXTAL / 2 Min. 20 6 6
2 2
fCPU = fXTAL x N N = 1.5 / 2 / 2.5 / 3 / 4 / 5 Min. 40 x N 10 10 - -
2 2
Unit
Max. 1000 - - 10 10
2 2
Max. 500 - - 6 6
3 2
Max. 100 x N - - 10 10
2 2
ns ns ns ns ns
- -
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 2. The input clock signal must reach the defined levels VIL and VIH2.
Figure 20 : External clock drive XTAL1
t1 t3 t4
VIL t2
VIH2
tOSC 56/74
ST10F168
20.5.9 - Memory Cycle Variables The tables below use three variables which are derived from the BUSCONx registers and which represent the special characteristics of the programmed memory cycle. The following table describes how these variables are computed.
Symbol tA tC tF ALE Extension Memory Cycle Time wait states Memory Tristate Time Description Values TCL x 2TCL x (15 - ) 2TCL x (1 - )
20.5.10 - Multiplexed Bus VDD = 5V 10%, VSS = 0V, for Q6 version : TA = -40, +85C and for Q3 version TA = -40, + 125C, CL = 100pF, ALE cycle time = 6 TCL + 2tA + tC + tF (120ns at 25MHz CPU clock without wait states), unless otherwise specified. Table 24 : Multiplexed bus characteristics
Maximum CPU Clock 25MHz Minimum t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t22 CC ALE high time CC Address setup to ALE CC Address hold after ALE CC ALE falling edge to RD, WR (with RW-delay) CC ALE falling edge to RD, WR (no RW-delay) CC Address float after RD, WR 1 (with RW-delay) CC Address float after RD, WR 1 (no RW-delay) CC RD, WR low time (with RW-delay) CC RD, WR low time (no RW-delay) SR RD to valid data in (with RW-delay) SR RD to valid data in (no RW-delay) SR ALE low to valid data in SR Address / Unlatched CS to valid data in SR Data hold after RD rising edge SR Data float after RD CC Data valid to WR
1
Symbol
Parameter
Variable CPU Clock 1/2 TCL = 1 to 25MHz Minimum TCL - 10 + tA TCL - 16+ tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - 2TCL - 20 + tC Maximum - - - - - 6 TCL + 6 - - 2TCL - 20+ tC 3TCL - 20+ tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF -
Unit
Maximum - - - - - 6 26 - - 20 + tC 40 + tC 40 + tA + tC 50 + 2tA + tC - 26 + tF -
10 + tA 4 + tA 10 + tA 10 + tA -10 + tA - - 30 + tC 50 + tC - - - - 0 - 20 + tC
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 24 : Multiplexed bus characteristics (continued)
Maximum CPU Clock 25MHz Minimum t23 t25 t27 t38 t39 t40 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t54 t56 CC Data hold after WR CC ALE rising edge after RD, WR CC Address / Unlatched CS hold after RD, WR CC ALE falling edge to Latched CS SR Latched CS low to Valid Data In CC Latched CS hold after RD, WR CC ALE fall. edge to RdCS, WrCS (with RW delay) CC ALE fall. edge to RdCS, WrCS (no RW delay) CC Address float after RdCS, WrCS 1 (with RW delay) CC Address float after RdCS, WrCS 1 (no RW delay) SR RdCS to Valid Data In (with RW delay) SR RdCS to Valid Data In (no RW delay) CC RdCS, WrCS Low Time (with RW delay) CC RdCS, WrCS Low Time (no RW delay) CC Data valid to WrCS SR Data hold after RdCS SR Data float after RdCS
1
Symbol
Parameter
Variable CPU Clock 1/2 TCL = 1 to 25MHz Minimum 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF -4 - tA - 3TCL - 14 + tF TCL - 4 + tA -4 + tA - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14+ tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF Maximum - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 0 TCL 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF - -
Unit
Maximum - - - 10 - tA 40 + tC + 2tA - - - 0 20 16 + tC 36 + tC - - - - 20 + tF - -
26 + tF 26 + tF 26 + tF -4 - tA - 46 + tF 16 + tA -4 + tA - - - - 30 + tC 50 + tC 26 + tC 0 - 20 + tF 20 + tF
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CC Address hold after RdCS, WrCS CC Data hold after WrCS
Note: 1. Partially tested, guaranteed by design characterization.
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ST10F168
Figure 21 : External Memory Cycle : multiplexed bus, with / without read/write delay, normal ALE
CLKOUT
t5
ALE
t16
t25
t6
t38
t17
t40 t39 t27
CSx
t6
A23-A16
(A15-A8) BHE
t17
Address
t27
t16
Read Cycle BUS (P0)
t6m
Address
t7
t18
Data In Address
t8
RD
t10 t14 t12
t19
t13 t9
Write Cycle BUS (P0)
t11 t15 t23
Data Out
Address
t8
WR WRL WRH
t22 t12 t13
t9
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ST10F168
Figure 22 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE
CLKOUT
t5
ALE
t16
t25
t6
t38 t17 t39 t27
t40
CSx
t6
A23-A16
(A15-A8) BHE
t17
Address
t27
Read Cycle BUS (P0)
t6
Address
t7
Data In
t8 t9
RD
t10 t11 t14 t15 t12 t13
t18 t19
Write Cycle BUS (P0)
Address
Data Out
t23 t8 t9
WR WRL WRH
t10 t11 t22
t13
t12
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ST10F168
Figure 23 : External Memory Cycle: multiplexed bus, with / without read/write delay, normal ALE, read/write chip select
CLKOUT
t5
ALE
t16
t25
t6
A23-A16
(A15-A8) BHE
t17
Address
t27
t16
Read Cycle BUS (P0)
t6
Address
t7
t51
Data In Address
t42
RdCSx
t44 t46 t48
t52
t49 t43
Write Cycle BUS (P0)
t45 t47 t56
Data Out
Address
t42
WrCSx
t50 t48 t49
t43
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ST10F168
Figure 24 : External Memory Cycle: multiplexed bus, with / without read/write delay, extended ALE, read/write chip select
CLKOUT
t5
ALE
t16
t25
t6
A23-A16
(A15-A8) BHE
t17
Address
t54
Read Cycle BUS (P0)
t6
Address
t7
Data In
t42 t43
RdCSx
t44 t45 t46 t48 t47 t49
t18 t19
Write Cycle BUS (P0)
Address
Data Out
t42 t43
WrCSx
t44 t45 t50
t56
t48 t49
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ST10F168
20.5.11 - Demultiplexed Bus VDD = 5V 10%, VSS = 0V, for Q6 version : TA = -40, +85C and for Q3 version TA = -40, +125C, CL = 100pF, ALE cycle time = 4 TCL + 2tA + tC + tF (80ns at 25MHz CPU clock without wait states), unless otherwise specified. Table 25 : Demultiplexed bus characteristics
Maximum CPU Clock = 25MHz Minimum t5 t6 t80 t81 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22 t24 t26 t28 CC ALE high time CC Address setup to ALE CC Address / Unlatched CS setup to RD, WR (with RW-delay) CC Address / Unlatched CS setup to RD, WR (no RW-delay) CC RD, WR low time (with RW-delay) CC RD, WR low time (no RW-delay) SR RD to valid data in (with RW-delay) SR RD to valid data in (no RW-delay) SR ALE low to valid data in SR Address / Unlatched CS to valid data in SR Data hold after RD rising edge SR Data float after RD rising edge (with RW-delay)1 2 SR Data float after RD rising edge (no RW-delay)1 2 CC Data valid to WR CC Data hold after WR CC ALE rising edge after RD, WR CC Address / Unlatched CS hold after RD, WR 3 10 + tA 4 + tA 30 + 2tA 10 + 2tA 30 + tC 50 + tC - - - - 0 - - 20 + tC 10 + tF -10 + tF 0 (no tF) -5 + tF (tF > 0) -5 + tF -4 - tA Maximum - - - - - - 20 + tC 40 + tC 40 + tA + tC 50 + 2tA + tC - 26 + tF 10 + tF - - - - Variable CPU Clock 1/2 TCL = 1 to 25MHz Minimum TCL - 10+ tA TCL - 16+ tA 2TCL - 10 + 2tA TCL -10 + 2tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 - - 2TCL- 20 + tC TCL - 10+ tF -10 + tF Maximum - - - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF + 2tA1 TCL - 10 + tF + 2tA1 - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter
Unit
-5 + tF (tF > 0)
- 10 - tA -5 + tF -4 - tA - 10 - tA ns ns
0 (no tF)
t28h CC Address / Unlatched CS hold after WRH t38 CC ALE falling edge to Latched CS
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ST10F168
Table 25 : Demultiplexed bus characteristics (continued)
Maximum CPU Clock = 25MHz Minimum t39 t41 t82 t83 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57 SR Latched CS low to Valid Data In CC Latched CS hold after RD, WR CC Address setup to RdCS, WrCS (with RW-delay) CC Address setup to RdCS, WrCS (no RW-delay) SR RdCS to Valid Data In (with RW-delay) SR RdCS to Valid Data In (no RW-delay) CC RdCS, WrCS Low Time (with RW-delay) CC RdCS, WrCS Low Time (no RW-delay) CC Data valid to WrCS SR Data hold after RdCS SR Data float after RdCS (with RW-delay) 2 SR Data float after RdCS (no RW-delay) 2 CC Address hold after RdCS, WrCS CC Data hold after WrCS - 6 + tF 26 + 2tA 6 + 2tA - - 30 + tC 50 + tC 26 + tC 0 - - -10 + tF 6 + tF Maximum 40 + tC + 2tA - - - 16 + tC 36 + tC - - - - 20 + tF 0 + tF - - Variable CPU Clock 1/2 TCL = 1 to 25MHz Minimum - TCL - 14 + tF 2TCL - 14 + 2tA TCL -14 + 2tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - - -10 + tF TCL - 14 + tF Maximum 3TCL - 20 + tC + 2tA - - - 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol
Parameter
Unit
Notes: 1. RW-delay and tA refer to the following bus cycle. 2. Partially tested, guaranteed by design characterization. 3. Read data is latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles.
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ST10F168
Figure 25 : External Memory Cycle: demultiplexed bus, with / without read/write delay, normal ALE
CLKOUT
t5
ALE
t16
t26
t6 t38
CSx
t17 t39
t41 t41u 1)
t6
A23-A16
(A15-A8) BHE
t17
Address
t28
Read Cycle Data Bus (P0)
t18
Data In
t80 t81
RD
t14 t15 t21
t20
t12 t13
Write Cycle Data Bus (P0)
Data Out
t80 t81
WR WRL WRH
t22
t24
t12 t13
Note: 1. Un-latched CSx = t41u = t41 - TCL = -14 + tF.
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ST10F168
Figure 26 : External Memory Cycle: demultiplexed bus, with / without read/write delay, extended ALE
CLKOUT
t5
ALE
t16
t26
t6 t38 t17 t39
CSx
t41 t28
t6
A23-A16
(A15-A8) BHE
t17
Address
t28
Read Cycle Data Bus (P0)
t18
Data In
t80 t81
RD
t14 t15 t21
t20
t12
Write Cycle Data Bus (P0)
t13
Data Out
t80 t81
WR WRL WRH
t22
t24
t12 t13
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ST10F168
Figure 27 : External Memory Cycle: demultiplexed bus, with / without read/write delay, normal ALE, read/write chip select
CLKOUT
t5
ALE
t16
t26
t6
A23-A16
(A15-A8) BHE
t17
Address
t55
Read Cycle Data Bus (P0)
t51
Data In
t82 t83
RdCsx
t46 t47
t53 t68
t48 t49
Write Cycle Data Bus (P0)
Data Out
t82 t83
WrCSx
t50
t57
t48 t49
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ST10F168
Figure 28 : External Memory Cycle: demultiplexed bus, no read/write delay, extended ALE, read/write chip select
CLKOUT
t5
ALE
t16
t26
t6
A23-A16
(A15-A8) BHE
t17
Address
t55
Read Cycle Data Bus (P0)
t51
Data In
t82 t83
RdCsx
t46 t47 t68
t53
t48 t49
Write Cycle Data Bus (P0)
Data Out
t82 t83
WrCSx
t50
t57
t48 t49
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ST10F168
20.5.12 - CLKOUT and READY VDD = 5V 10%, VSS = 0V, for Q6 version : TA = -40, +85C and for Q3 version TA = -40, +125C, CL = 100pF, unless otherwise specified Table 26 : CLKOUT and READY characteristics
Max. CPU Clock 25MHz Minimum t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60 CC CLKOUT cycle time CC CLKOUT high time CC CLKOUT low time CC CLKOUT rise time CC CLKOUT fall time CC CLKOUT rising edge to ALE falling edge SR Synchronous READY setup time to CLKOUT SR Synchronous READY hold time after CLKOUT SR Asynchronous READY low time SR Asynchronous READY setup time 1 SR Asynchronous READY hold time 1 40 14 10 - - -3 + tA 14 4 54 14 4 0 Maximum 40 - - 4 4 +7 + tA - - - - - 0 + 2tA + tC + tF
2
Symbol
Parameter
Variable CPU Clock 1/2 TCL = 1 to 25MHz Minimum 2TCL TCL - 6 TCL - 10 - - -3 + tA 14 4 2TCL + 14 14 4 0 Maximum 2TCL - - 4 4 7 + tA - - - - - TCL - 20 + 2tA + tC + tF 2
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
SR Async. READY hold time after RD, WR high (Demultiplexed Bus) 2
Notes: 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
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ST10F168
Figure 29 : CLKOUT and READY
Running cycle 1) READY wait state MUX / Tristate 6)
CLKOUT
t32 t30 t34
t33 t31 t29
ALE
7)
RD, WR
2)
Synchronous READY Asynchronous READY
t35
3)
t36
t35
3)
t36
t58
3)
t59
t58
3)
t59
t604)
t37
5) 6)
Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t 37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state may be inserted here. For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC wait state this delay is zero. 7. The next external bus cycle may start here.
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ST10F168
20.5.13 - External Bus Arbitration VDD = 5V 10%, VSS = 0V, for Q6 version : TA = -40, +85C and for Q3 version TA = -40, +125C, CL = 100pF, unless otherwise specified.
Max. CPU Clock 25MHz Minimum t61 t62 t63 t64 t65 t66 t67 SR HOLD input setup time to CLKOUT CC CLKOUT to HLDA high or BREQ low delay CC CLKOUT to HLDA low or BREQ high delay CC CSx release 1 CC CSx drive CC Other signals release CC Other signals drive
1
Symbol
Parameter
Variable CPU Clock 1/2 TCL = 1 to 25MHz Minimum 20 - - - -4 - -4 Maximum - 20 20 20 24 20 24
Unit
Maximum - 20 20 20 24 20 24
20 - - - -4 - -4
ns ns ns ns ns ns ns
Note: 1. Partially tested, guaranted by design characterization.
Figure 30 : External bus arbitration, releasing the bus
CLKOUT
t61
HOLD
t63
HLDA
1)
t62
BREQ
2)
t64
3)
CSx (P6.x)
1)
t66
Others
Notes: 1. The ST10F168 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pullup) after t64.
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ST10F168
Figure 31 : External bus arbitration, (regaining the bus)
CLKOUT
2)
t61
HOLD
t62
HLDA
t62
BREQ
t62
1)
t63
t65
CSx (P6.x)
t67
Others
Notes: 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F168 requesting the bus. 2. The next ST10F168 driven bus cycle may start here.
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ST10F168
21 - PACKAGE MECHANICAL DATA Figure 32 : Package Outline PQFP144 (28 x 28mm)
A A2 144 e A1 109 0,10 mm .004 inch SEATING PLANE 108 B 36 73 E3 E1 E 37 D3 D1 D 72
c
1
L1
Millimeters 1 Dimensions Minimum A A1 A2 B c D D1 D3 e E E1 L L1 K 30.95 27.90 0.65 0.25 3.17 0.22 0.13 30.95 27.90 31.20 28.00 22.75 0.65 31.20 28.00 0.80 1.60 0 (Min.), 7 (Max.) 31.45 28.10 0.95 1.219 1.098 0.026 3.42 3.67 0.38 0.23 31.45 28.10 Typical Maximum 4.07 0.010 0.125 0.009 0.005 1.219 1.098 Minimum
L K
Inches (approx) Typical Maximum 0.160 0.133 0.144 0.015 0.009 1.228 1.102 0.896 0.026 1.228 1.102 0.031 0.063 1.238 1.106 0.037 1.238 1.106
Note: 1. Package dimensions are in mm. The dimensions quoted in inches are rounded.
22 - ORDERING INFORMATION
Sales type ST10F168-Q6 ST10F168-Q3 Temperature range -40C to 85C -40C to 125C Package PQFP144 (28 x 28mm) PQFP144 (28 x 28mm) 73/74
ST10F168
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - All Rights Reserved
F168Q3Q6.REF
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74
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